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| LSI 6 f 279 ompa MNs 6or C0RSCct Disc/CD-ROM Player MN66279RSC 1. Type Signal processing LSI for CDs (Compact Discs) 2. Overview MN662790RSC is a signal processing LSI for CDs which is applicable to 4x-speed playback. It incorporates optical servo (focus, tracking and traverse servos) processing function, digital signal processing function (EFM demodulation and error correction), digital servo processing function for spindle motor, a digital filter and D/A converter. All the processing functions after the head amplifier (RF amplifier) are incorporated into a single chip. In addition, it incorporates clock generation and error correction circuits to increase the playability and is applicable to video CD playback. 3. Functions and features (Optical servo) Focus (Fo), tracking (Tr) and traverse (TRV) servos (fS: Fo 44.1 kHz, Tr 44.1 kHz) Automatic adjustment functions (Fo/Tr gain, Fo/Tr offset, Fo/Tr balance) On-chip D/A converter for drive voltage output Provided with a countermeasure for dropout Provided with anti-shock function Provided with track cross detecting function On-chip track cross counter (Digital signal processing) Containing DSL and PLL Provided with a frame synchronous detection/protection/interpolation Subcode data processing Q-data CRC check On-chip Q-data register CD-TEXT interface function On-chip CD-TEXT register (144 bits 2) CIRC error correction C1 decoder double error correction C2 decoder triple error correction, quadruple error correction On-chip de-interleaving 16K RAM Audio data interpolation processing 4-sampling average value interpolation and previous value hold Digital attenuation (256 levels) Soft attenuation (256 levels) Soft muting Digital audio interface (EIAJ format) Audio data serial interface (Input/Output) Microcomputer serial interface General-purpose I/O port (4 pins) Audio data peak level detection function Publication data: July 2002 SDD00025AEM 1 MN662790RSC (Spindle motor servo) CLV digital servo Servo gain setting function (Audio Circuit) 8x-oversampling digital filter On-chip D/A converter (1-bit DAC) On-chip differential OP amp (2nd-order low-pass filter) (Others) 4x-speed playback Disc rotation synchronizing playback (jitter-free) function (4x-speed 50 ) Oscillation stop mode Power management mode Playback pitch control function 4. Package 80-pin quad flat package (LQFP080-P-1414A) SDD00025AEM 2 MN662790RSC BYTCK/TRVSTP GIO1/CLDCK GIO2/FCLK IPFLAG FLAG CLVS CRC DEMPH RESY/FLAG6 IOSEL TEST AVDD1 OUTL AVSS1 OUTR RSEL/GIO3 VCC5V PSEL MSEL SSEL 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD X2 X1 VSS SBCK SUBC VCOF2 PCK/DSLB EFM/CK384 AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF W V EL DSLBDA PLLF2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 LD O N BDO RFDET TRCRS OFT TEST3 RFENV TE FE TBAL FBAL VREF FOD TRD VDETMON ECS ECM PC TV D TEST2 BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK/GIO0 SUBQ DMUTE STAT RST SMCK CSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1 Pin Assignment SDD00025AEM 3 MN662790RSC 5. Block diagram DIGITAL DE-EMPHASIS 8xOVERSAMPLING DIGITAL FILTER LRCKIN(MSEL) BCLKIN(SSEL) SRDATAIN(PSEL) 1-bit DAC PWM LOGIC AVSS1 AVDD1 OUTR PWM (L) PWM (R) OUTL IOSEL CLVS CRC BLKCK GIO1(CLDCK) SBCK SUBC DEMPH DEMODULATION CD-TEXT BUFFER SYNCA@ INTERPOLATION 16K SRAM FLAG6(RESY) SSEL SQCK(GIO0) SUBQ AVSS2 AVDD2 PCK(DSLB) EFM(CK384) PLLF PLLF2 DSLF IREF DRF ARF RSEL(GIO3) PSEL MLD MCLK MDATA D/A CONVERTER VCOF2 VCOF BYTCK(TRVSTP) SMCK GIO2(FCLK) CSEL MSEL X2 X1 STAT A/D CONVERTER INPUT PORT SERVO TIMING GENERATOR VCO SUBCODE BUFFER FLAG IPFLAG DIGITAL AUDIO INTERFACE TX DEMODULATION CIRC ERROR CORRECTION SERVO ECM ECS PC DE-INTERLEAVE SUBCODE CLV INTERPOLATION SOFT MUTING DIGITAL ATTENUATION DSL / PLL VCO LRCK SRDATA BCLK DMUTE DSLBDA VDETMON VREF TVD TRD FOD TBAL FBAL TLOCK FLOCK LDON EFM TIMING GENERATOR PITCH CONTROL MICROCOMPUTER INTERFACE SERVO CPU OUTPUT PORT WVEL SENSE RFENV VCC5V VDD VSS DVDD1 DVSS1 RST TEST FE RFDET TRCRS TEST3 BDO OFT TE SDD00025AEM 4 MN662790RSC 6. Pin descriptions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK I/O O O O I I O I I I O O O O Pin for 5-V input Bit clock output for SRDATA L/R identification signal output Serial data output Power supply for digital circuits Ground for digital circuits Digital audio interface output signal Microcomputer command clock signal input (Latches the data at a rising edge) Microcomputer command data signal input Microcomputer command load signal input L: Load Function Sense signal output (OFT, FESL, ACEND, AJEND, SFG) Focus servo pull-in signal Tracking servo pull-in signal (L: Pull-in status) (L: Pull-in status) Subcode block clock signal (fBLKCK 75 Hz) At command execution: CD-TEXT data reading enable signal (DQSY) output At default value: External clock input for subcode Q register At command execution: General-purpose I/O port In CD-TEXT 2 mode: Clock input for TEXT data reading Subcode Q-data output In CD-TEXT 2 mode: TEXT data output Muting input H: Mute 14 SQCK/ GIO0 I 15 16 17 SUBQ DMUTE STAT O I O Status signal (CRC, STCNT, CLVS, TTSTOP, JCLVS, SQOK, FLAG6, SENSE, FLOCK, TLOCK, rotating speed data, FCLV, SUBQ, SYFLG) In CD-TEXT 3 mode: Subcode Q and TEXT data output Reset input 8.4672-MHz clock signal output at MSEL 4.2336-MHz clock signal output at MSEL Oscillation frequency selection pin H L H: 33.8688 MHz L: 16.9344 MHz L: Reset 18 19 RST SMCK I O 20 CSEL I SDD00025AEM 5 MN662790RSC Pin for 5-V input TEST pin 2 Traverse drive output Spindle motor ON signal output L: ON (default) 3-state output No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol TEST2 TV D PC ECM ECS VDETMON TRD FOD VREF FBAL TBAL FE TE RFENV TEST3 OFT TRCRS RFDET BDO LDON PLLF2 DSLBDA WVEL ARF I/O O O O O O O O O I O O I I I I I I I I O I/O O O I Function Normal: OPEN Spindle motor drive signal (Forced mode output) Spindle motor drive signal (Servo error signal output) Vibration detection monitor output Tracking drive output Focus drive output Reference voltage for D/A output stage (TVD, ECS, TRD, FOD, FBAL, TBAL, TOFS) Focus balance adjustment output Tracking balance adjustment output Focus error signal input Tracking error signal input RF envelope signal input TEST pin 3 Off track signal input Track cross signal input RF detection signal input Dropout signal input Laser ON signal output (Analog input) (Analog input) (Analog input) Normal: Fixed to "L" H: Off track (Analog input) L: Detection H: Dropout H: ON Selector pin for PLL loop filter characteristics DSL balance output (D/A output) 2x-speed status signal output RF signal input L: 2x-speed SDD00025AEM 6 MN662790RSC Pin for 5-V input Reference current input pin Bias pin for DSL DSL loop filter pin PLL loop filter pin VCO loop filter pin Power supply for analog circuits (For DSL, PLL, D/A output stage and A/D) Ground for analog circuits (For DSL, PLL, D/A output stage and A/D) At IOSEL = H: EFM signal output At IOSEL = L: 16.9344-MHz clock output for crystal oscillation 384fS output for signal processing (VCO clock output in jitter-free operation) (Select crystal oscillation or signal processing with command setting) No. 45 46 47 48 49 50 51 Symbol IREF DRF DSLF PLLF VCOF AVDD2 AVSS2 I/O I I I/O I/O I/O I I Function 52 EFM/ CK384 PCK/ DSLB VCOF2 O 53 54 O I/O PLL extraction clock output or DSL balance output (PWM output) (fPCK=4.3218 MHz) VCO loop filter pin for the digital servo clock generation at 33.8688 MHz The external circuit is required for crystal oscillation at 16.9344 MHz. Subcode serial output In CD-TEXT 1 mode: TEXT data output Clock input for subcode serial output In CD-TEXT 1 mode: Clock input for TEXT data reading Ground for oscillation circuit Crystal oscillation circuit input pin Crystal oscillation circuit output pin Power supply for oscillation circuit At IOSEL = H: Byte clock signal output At IOSEL = L: Traverse stop signal output (f 16.9344 MHz, 33.8688 MHz) (f 16.9344 MHz, 33.8688 MHz) 55 SUBC O 56 57 58 59 60 61 SBCK VSS X1 X2 VDD BYTCK/ TRVSTP GIO1/ CLDCK GIO2/ FCLK IPFLAG FLAG I I I O I O H: STOP mode 62 O At default value: General-purpose I/O port At command execution: Subcode frame clock signal output (fCLDCK=7.35 kHz) At default value: General-purpose I/O port At command execution: Crystal frame clock signal output (fFCLK=7.35 kHz) Interpolation flag signal output Flag signal output H: Interpolation 63 64 65 O O O SDD00025AEM 7 MN662790RSC No. 66 Symbol CLVS I/O O Pin for 5-V input Function Spindle servo phase synchronous status signal output H: CLV L: Rough servo H: OK L: NG H: ON 67 68 69 CRC DEMPH RESY/ FLAG6 O O O At default value: Subcode CRC check result output De-emphasis detecting signal output At IOSEL = H: At IOSEL = L: Frame re-sync signal RESY output H: Synchronous L: Asynchronous RAM address reset signal FLAG6 output for error correction and de-interleave L: Address reset generated 70 71 72 73 74 75 76 IOSEL TEST AVDD1 OUTL AVSS1 OUTR RSEL/ GIO3 I I I O I O I Mode selector pin Test pin Power supply for analog circuits L-ch audio output Ground for analog circuits R-ch audio output At default value: RF signal polarity specification pin When the bright level is "H", RSEL=H. When the bright level is "L", RSEL=L. At command execution: General-purpose I/O port RF signal polarity is specified with command setting. In CD-TEXT 1 or 2 mode: TEXT data reading enable signal (DQSY) output (For audio output stage) (Commonly used for L-ch and R-ch) (Normal: H) (For audio output stage) (Commonly used for L-ch and R-ch) 77 78 VCC5V PSEL I I 5-V power supply applied to pins for 5-V input At IOSEL = H: Test pin At IOSEL = L: SRDATA input (Normal: L) 79 MSEL I At IOSEL = H: SMCK pin output frequency selector pin H: SMCK = 8.4672 MHz L: SMCK = 4.2336 MHz At IOSEL= L: LRCK input H: L-ch data, L: R-ch data SMCK = Fixed at 4.2336 MHz At IOSEL = H: SUBQ pin output mode selector pin H: Q-code buffer working mode L: CLDCK synchronous mode At IOSEL = L: BCLK input Q-code buffer working mode fixed 80 SSEL I SDD00025AEM 8 MN662790RSC 7. Function description (Table of contents) 7-0. Contents of functions amended from MN662748 7-0 (1) 7-0 (2) 7-0 (3) 7-0 (4) Digital servo section Signal processing section Digital filter (DF) and D/A converter (DAC) sections The whole system P 10 P 10 P 11 P 12 P 12 7-1. Microcomputer interface 7-1 (1) 7-1 (2) 7-1 (3) 7-1 (4) 7-1 (5) List of microcomputer commands Initialization Data setting for servos Data setting in signal processing section Automatic adjustment P 14 P 15 P 19 P 21 P 45 P 57 P 58 P 58 P 59 P 59 P 61 P 65 P 66 P 70 P 71 P 71 P 71 P 72 7-2. I/O timing 7-2 (1) Serial data output 7-2 (2) Serial data output with de-emphasis function ON 7-2 (3) Serial data input format 7-2 (4) Subcode interface 7-2 (5) EDATA error rate monitor function 7-2 (6) CD-TEXT interface 7-2 (7) Digital PLL setting 7-2 (8) Video CD setting 7-2 (9) Digital audio interface Bit V control 7-2 (10) Audio output MUTE 7-2 (11) Error correction SDD00025AEM 9 MN662790RSC 7-0. Contents of functions amended from MN662748 7-0 (1) Digital servo section 1) Initialization Initialization with SYS command after the standby time (0.1 s) preset by the on-chip timer has elapsed 2) Automatic adjustment Abolishment of Tr offset external feedback adjustment Fo/Tr offset adjustments batch processing only Setting of the convergence gain for Fo balance adjustment Abolishment of Tr rough gain adjustment with TROFF Selection of the convergence conditions for Tr balance adjustment Hunting preventive function in Fo balance adjustment (1/8, 1/4, 1/32, 1/16) 3) Servo Servo sampling frequency: 44.1 kHz Vibration detection with software TRV dead-zone amplifier mode selectable Unified Tr servo output (TRD and KICK) Unified TRV servo output (TVD and TRV) TVD output gain selectable Fo servo filter Z-N setting (N: Fixed to 2) Selecting Fo servo dropout processing (0 mute only) Selecting Fo disc detecting frequency (5.4 Hz, 2.6 Hz) Tr servo output stage noise shaver ON/OFF (Fixed to ON) Selecting Tr servo dropout processing (0 mute only) Selecting TRV loop filter (Type A only) Smoothing TRV servo output OFT input noise filter turned ON/OFF with a command Setting of high-speed Fo pull-in operation when turning Fo ON from OFF state Setting of dropout processing during KICK operation Trigger function at vibration detection Abolishment of Fo servo's perfect integral and limited characteristics selection (Perfect integral characteristic only) Abolishment of Tr servo's perfect integral and limited characteristics selection (Perfect integral characteristic only) Change of servo parameter exponent part format (FEXP, TEXP) 4) Access TCNT (track count move) processing with software Outputting TRD during TCNT (track count move) (0 only) 5) DTMS, DTSM Possible to set Tr gain constant limiter arbitrarily for initial Tr gain constant and Tr fine gain adjustments Possible to set Fo gain constant limiter arbitrarily for initial Fo gain constant and Fo fine gain adjustments Possible to set band-pass filter constants and a detecting level for vibration detection SDD00025AEM 10 MN662790RSC 7-0 (2) Signal processing section 1) Signal processing over the system Applicable for VIDEO CDs Error correction method Selectable between double (C1) and triple (C2) corrections, and double (C1) and quadruple (C2) corrections C1 flag discrimination condition at C2 correction selectable PLL circuit for VIDEO CDs (Digital PLL) Other functions Audio interpolation processing 4-sampling interpolation Addition of CD-TEXT output format 4 mode Peak data output function (Same as the specification for MN662780) Audio output level attenuation function Pitch control function ( 50 of 1x-, 2x- and 4x-speed) Error flag counting function (selectable between FLAG0 and IPFLAG) TX output generation from audio DAC external input data (Conventional method is also selectable) 2) DSL, PLL PLLF current selection mode ( 1, 0.75, PLL frequency dividing function Digital PLL control Charge pump current adjusting function 3) Digital audio interface (TX) Bit V control of TX output Generation of TX output from DF input data 4) Spindle servo CLV synchronization establishment detecting flag 0.5, 1.25) SDD00025AEM 11 MN662790RSC 7-0 (3) Digital filter (DF) and D/A converter (DAC) sections Newly added digital filter calculation constants 1-bit D/A converter 7-0 (4) The whole system PMCK and PLAY pins eliminated VCC5V pin for 5-V input added 3.3-V operation of internal circuit Digital input pins for 5-V input SDD00025AEM 12 MN662790RSC IOSEL IOSEL SERV EFM BYTCK RESY L L H LRCK BCLK SRDATA PSEL SSEL MSEL PSEL SSEL MSEL SERV EFM BYTCK RESY LRCK BCLK SRDATA Setting the LSI Operation Mode by the IOSEL Pin SIGNAL PROCESSOR SIGNAL PROCESSOR SDD00025AEM PSEL SSEL MSEL EFM CK384 BYTCK TRVSTP RESY FLAG6 EFM CK384 BYTCK TRVSTP RESY FLAG6 L L H PSEL SSEL MSEL DF/ DAC DF/ DAC 13 MN662790RSC 7-1. Microcomputer interface Each mode can be set by inputting the 16-bit data (D15 to 0) and 8-bit command (B7 to 0) starting from the MSB in 3 inputs of MDATA, MCLK and MLD at the timing as shown in Figure 7-1-1. MSB D15 D14 D13 LSB D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 Note Data is determined at the "L" level of MLD. MDATA, MCLK and MLD are invalid while RST is "L". All commands are initialized by setting RST to "L". While MLD is set to "L", MCLK will be canceled if it rises. Timing B2 B1 B0 Min. Min. Min. Min. Min. 600 ns Min. Min. 300 ns 300 ns 300 ns 300 ns 600 ns 300 ns Max. 100 s Figure 7-1-1 SDD00025AEM 14 MN662790RSC 7-1 (1) List of microcomputer commands (1-1) Servo processor Table 7-1-1 (1) Control Target Initialization Automatic adjustment MDATA Symbol B7 B6 B5 B4 B3 B2 B1 B0 SYS System setting RESERVED Function SENSE output SFG At reset Data 16 bits Chapter Fo balance adjustment Stopping automatic adjustment Offset adjustment AOC (Fo, Tr) RESERVED ABC2 Tr balance adjustment AGC1 Fo rough gain adjustment AGC2 Tr rough gain adjustment FAGC Fo fine gain adjustment TAGC Tr fine gain adjustment ABC1 ADA DTMS Data write DTSM Data read STB DDT TO F PLY PLY2 Standby RESERVED Disc detection Fo ON, Tr OFF Fo ON, Tr ON Fo ON, Tr ON (TRVSTP disabled) TRV stop RESERVED TRV forward feed TRV reverse feed TRV play Stopping access operation Kick Track count move AJEND AJEND AJEND AJEND AJEND AJEND AJEND AJEND WTEND DATA OFT FESL FESL OFT OFT 16 bits 8 bits Data setting Optical servo TRV servo TV S TV F TV R TV P No change Access ACA KICK TCNT ACEND ACEND ACEND 16 bits 16 bits SDD00025AEM 15 MN662790RSC (1-2) Signal processing Table 7-1-1 (2) Control Target MDATA Symbol B7 B6 B5 B4 B3 B2 B1 B0 RESERVED RESERVED Turntable ON (H) Turntable OFF (L) Free-running Acceleration Deceleration Normal play Digital I/F Bit C (28) SET Digital I/F Bit C (28) RESET Digital I/F Bit C (29) SET Digital I/F Bit C (29) RESET Normal output (0dB) Soft muting Digital attenuation Soft attenuation NOS DOS WVEL=L Normal-speed playback WVEL=H 2x-speed playback LRCK signal (R-ch=L, L-ch=H) LRCK signal (R-ch=H, L-ch=L) Audio mode ( ) Audio mode ( ) CD-ROM mode TX pin output enabled TX pin output disabled ("L" is fixed) Digital I/F category code = CD mode Digital I/F category code = general mode Audio output control (I) Digital/Audio I/F control General-purpose I/O port control Spindle control Audio output control (II) Audio output control (III) CLV speed setting RESERVED DSL and PLL controls (I) DSL and PLL controls (II) Digital PLL control 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits Function Data At Chapter reset Spindle TTO N TTOFF STOP ACC BRAKE PLAY TX output Audio output Audio output TX output SDD00025AEM 16 MN662790RSC Table 7-1-1 (3) Control Target SRDATA Audio output STAT pin output MDATA B7 B6 B5 B4 B3 B2 B1 B0 AL3 to 0 AL7 to 4 Symbol Function Data At reset Chapter Attenuation level (lower 4 bits) Attenuation level (upper 4 bits) STAT output CRC STAT output STCNT STAT output CLVS STAT output TTSTOP (during TTOFF) STAT output JCLVS (during TTON) STAT output SQOK STAT output switching STAT output disc rotating speed STAT output FCLV STAT output SUBQ STAT output SYFLG STAT output EDATA 3 bits 16 bits SDD00025AEM 17 MN662790RSC SENSE signal SENSE signal can be monitored through STAT pin. The meaning of SENSE signal varies with the input command. The meanings are described below. OFT FESL Off-track input signal is output as it is. It is set to "H" when the absolute value of the focus error signal amplitude exceeds 30 [LSB] by executing the disc detecting command. It is set to "L" when the access terminates and the pull-in operation of the tracking servo starts. It is set to "L" when automatic adjustment terminates. It is set to "L" when data write terminates normally. The contents of the RAM of the specified address is output beginning with MSB by inputting MCLK a minimum of 50 ms after MLD is set to "L" with the data read command, DTSM, sent out for data reading. Refer to Figure 7-1-4. ACEND AJEND WTEND DATA Disc detection Fo ON Tr ON Fo fine AGC KICK FESL OFT AJEND ACEND (STAT pin) End of automatic adjustment Figure 7-1-2 Switching of SENSE output End of KICK SDD00025AEM 18 MN662790RSC 7-1 (2) Initialization After clearing RST, the system waits for a data write command (DTMS) and SYS command. 1) After clearing RST, execute the data write command first. The data write command is composed of the following three bytes, which is different from the regular format (see page 22). 15 7 7 14 6 6 13 5 5 12 4 4 11 3 3 10 2 2 9 1 1 8 0 0 That is, SET0 (various system settings) data is stored in the upper 8 bits of the 16-bit data, and VSET (anti-vibration mode selection) data is stored in the lower 8 bits. 2) After the data write command (DTMS) is processed, the SENSE signal (WTEND) is set to "L" and it is in the standby status for the SYS command. Unlike conventional models, no system settings are possible with the SYS command. This is due to the expansion of the DTMS/DTSM functions. Execute the following command, however, after checking that the SENSE signal is set to "L". This is for the protocol assurance of the SENSE signal with the mechanical controller. When the SYS command MDATA 1111 0101 is accepted, the SENSE signal is set to "H" and processing of the SYS command starts. When the processing completes, the SENSE signal is set to "L" to enter the normal operation loop. Table 7-1-2 indicates the default values of system setting. The default value of each item is changeable with the DTMS command. Note) If the data write command (DTMS) is not executed within 743 ms after starting the standby status for the data write command (DTMS) and the SYS command, the system setting is performed with the default value and enters the normal operation loop. Be aware that initial SET0 data and VSET data are written in a special format that is entirely different from the format used for writing usual data. In initial setting, SET0 and VSET are set at the same time only by sending a 3-byte command once, while in normal write, SET0 and VSET are set separately using a 3-byte command. Timing chart is shown in Figure 7-1-3. SDD00025AEM 19 MN662790RSC 743 ms max. 0.1 s (STAT Pin) DTMS SYS Other than S YS Figure 7-1-3 Timing chart in initial setting A 0.1-s standby time is not necessary to send the DTMS command and the SYS command after reset clearance. To ensure system stability after turning on the power, send the DTMS command and the SYS command after SENSE is set to "H". Table 7-1-2 Item Gain for tracking variable gain amp Gain for focus variable gain amp Output amplitude for focus search Fail-safe value for tracking servo Standby time after track count move Traverse drive constant Traverse drive dead-zone Optical servo Traverse servo 2x-speed mode Spindle servo TX pin output STAT pin output Default value 6 [dB] 12 [dB] 22 [LSB] 72 [LSB] 50 [ms] 2 24 [LSB] Standby Stop NOS Turntable OFF STOP (Free-running) Enabled CRC output Note To obtain the waveform shown in the above timing chart, the MLD pulse width should be 10 s or less. If it is more than the value, SENSE clear ("H" "L") by the SYS command in the above timing may not be performed. SDD00025AEM 20 MN662790RSC 7-1 (3) Data setting for servos [1] Data write (DTMS) Various features can be achieved by writing various characteristics of the optical servo system from an external microcomputer to this LSI. DTMS command is used to write the data such as servo parameters. (Applications) (A) Setting of automatic adjustment value (B) Setting of the optical servo loop characteristics including the characteristics for anti-vibration (C) Setting of gain crossover for the optical servo loop (D) Mode selection for anti-vibration (E) Various system settings (F) Various settings for optical servo system (MDATA format) D D A D A D A D A D A D1 A D0 A A : Data : Address (Label specified) : Command (DTMS) Note) Use the DTMS command in the STANDBY or PLAY mode. If you write data successively, wait at least 50 s after each data writing so that the microcomputer finishes DSP processing and becomes ready for writing next data. SDD00025AEM 21 MN662790RSC [2] Data read (DTSM) This LSI can read out the parameters such as automatic adjustment results of the optical servo with the DTSM command. (MDATA format) A7 A6 A5 A4 A3 A2 A1 A0 Address (Label specified) Command (DTSM) (Data output format) Input an address and a command, and after a lapse of 50 s or more since setting MLD=L, input MCLK, thus enabling to read data from STAT pin. (SENSE output) DTSM (STAT pin) Indefinite Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data 0 Min. 50 s Figure 7-1-4 Timing chart for reading data Note) Perform either in the STANDBY or PLAY mode. SDD00025AEM 22 MN662790RSC (List of DTMS addresses) Table 7-1-3 (1) Address (HEX) (A7 to A0) Label Application Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus balance automatic adjustment value Focus offset automatic adjustment value Tracking gain automatic adjustment value in normal-speed mode (for setting use) Tracking gain automatic adjustment value in normal-speed mode (for setting use) Reference page Tracking balance automatic adjustment value Tracking offset automatic adjustment value Focus phase compensation constant Focus low-band compensation constant Tracking phase compensation constant Tracking low-band compensation constant Focus phase compensation constant at vibration Focus low-band compensation constant at vibration Tracking phase compensation constant at vibration Tracking low-band compensation constant at vibration Gain crossover setting Mode selection for anti-vibration Various system settings Various system settings Various system settings Various system settings Focus gain disturbance amplitude Tracking gain disturbance amplitude Focus search amplitude Search direction Kick speed / Kick brake timing Traverse gain constant in tracking brake operation Fail-safe value for tracking servo Tracking balance disturbance adjustment value Various system settings Traverse drive dead-zone 25 25 25 25 25 25 25 25 26 26 26 26 26 26 26 26 28 29 31 32 33 35 25 25 38 38 39 40 38 38 34 40 SDD00025AEM 23 MN662790RSC Table 7-1-3 (2) Address (HEX) (A7 to A0) Label Application Focus gain constant mantissa part at vibration (for setting use) Focus gain constant exponent part at vibration (for setting use) Tracking gain constant mantissa part at vibration (for setting use) Tracking gain constant exponent part at vibration (for setting use) Focus gain constant upper limit mantissa part Focus gain constant upper limit exponent part Focus gain constant lower limit mantissa part Focus gain constant lower limit exponent part Tracking gain constant upper limit mantissa part Tracking gain constant upper limit exponent part Tracking gain constant lower limit mantissa part Tracking gain constant lower limit exponent part Track count and KICK noise elimination width Various system settings Inverted pulse width with tracking brake and servo control turned on Initial accelerating time with tracking brake turned on Convergence gain setting in fine gain adjustment KICK output level in normal operation Traverse output level KICK output level when servo is pulled in Vibration detecting level mantissa part Number of disturbance waves setting in fine gain adjustment Focus and tracking gains setting for normal gain Focus and tracking gains setting for forced gain-up Software reset Reference page 30 30 30 30 43 43 43 43 43 43 43 43 40 36 41 41 42 41 41 41 42 42 37 37 37 Do not write illegal data in any of the above addresses, otherwise the existing data in the address is overwritten and the operation of this LSI is not guaranteed. SDD00025AEM 24 MN662790RSC (A) Setting of automatic adjustment value FG0 FEXP0 FBAL FOFS FES TES (Focus gain mantissa part) (Focus gain exponent part) (Focus balance adjustment value) (Focus offset adjustment value) (Disturbance amplitude in focus gain adjustment) (Disturbance amplitude in tracking gain adjustment) , , , , TG0 TEXP0 TBAL TOFS (Tracking gain mantissa part) (Tracking gain exponent part) (Tracking balance adjustment value) (Tracking offset adjustment value) Table 7-1-3 (3) Data (D7 to D0) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) 00 01 F2 Function Focus gain constant (FG0) (8-bit mantissa) (1 to 255) Focus gain constant (FEXP0) (8-bit exponent) (16, 32, 64 and 128 only) (Focus gain constant = mantissa / exponent) Focus balance constant (FBAL) (8-bit 2' s complement) ( 128 to +127) Focus offset constant (FOFS) (8-bit 2' s complement) ( 128 to +127) Tracking gain constant (TG0) (8-bit mantissa) (1 to 255) Tracking gain constant (TEXP0) (8-bit exponent) (16, 32, 64 and 128 only) (Tracking gain constant = mantissa / exponent) Tracking balance constant (TBAL) (8-bit 2' s complement) ( 128 to +127) Tracking offset constant (TOFS) (8-bit 2' s complement) ( 128 to +127) Disturbance amplitude in focus gain adjustment (FES) (1 to 127) Disturbance amplitude in tracking gain adjustment (TES) (1 to 127) Setting at reset 128 32 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 02 03 04 05 0 0 128 64 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 06 07 16 0 0 85 D7 D6 D5 D4 D3 D2 D1 D0 17 85 SDD00025AEM 25 MN662790RSC (B) Setting of the optical servo characteristics including the characteristics for anti-vibration Gain constant Focus gain mantissa part FG Tracking gain mantissa part Focus gain exponent part FEXP Tracking gain exponent part TG TEXP Phase compensation and low-band compensation constant Focus phase compensation constant FC Tracking phase compensation constant TC Focus low-band compensation constant FR Tracking low-band compensation constant TR The above eight constants can be set by writing 8-bit data (0 to 127) directly with the microcomputer command. Structure K Z -1 R G + + Z -N fs of the focus system: 44.1 kHz fs of the tracking system: 44.1 kHz (fs of the low-band compensation filter is 22.05 kHz.) C + G (Z) G 1 1 Z 1 R (1 C Z) N G= TG TEXP TR 2 15 or FG FEXP FR 2 15 C= TC 128 or FC 128 R= or K 1 N in Z N can be replaced with : always 2 in case of the focus system. 1 in case of the tracking system. SDD00025AEM 26 MN662790RSC Setting of loop filter constants Table 7-1-3 (4) Data (D7 to D0) D7 D6 D7 D6 D7 D6 D7 D6 D5 D4 D5 D4 D5 D4 D5 D4 D3 D3 D3 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) 08 09 0A 0B F2 Function Focus phase compensation constant : FC (8-bit) (1 to 127) Focus low-band compensation constant : FR (8-bit) (1 to 127) Tracking phase compensation constant: TC (8-bit) (1 to 127) Tracking low-band compensation constant : TR (8-bit) (1 to 127) Focus phase compensation constant at vibration : FC2 (8-bit) (1 to 127) Focus low-band compensation constant at vibration : FR2 (8-bit) (1 to 127) Tracking phase compensation constant at vibration : TC2 (8-bit) (1 to 127) Tracking low-band compensation constant at vibration : TR2 (8-bit) (1 to 127) Setting at reset 117 64 122 64 D7 D6 D7 D6 D7 D6 D7 D6 D5 D4 D5 D4 D5 D4 D5 D4 D3 D3 D3 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 0C 0D 0E 0F 117 64 122 64 SDD00025AEM 27 MN662790RSC (C) Setting of gain crossover for optical servo loop Before performing focus and tracking automatic adjustments, gain crossover after automatic adjustment can be determined by writing data to the label name GSET (address: 10h) according to the table below. In the automatic gain adjustment, disturbance is input to the servo loop, and gain is increased or decreased according to the GSET setting after adjusting the gain so that the feedback gain at the frequency becomes 0 dB (gain crossover is equal to the frequency). (Setting for focus system) Data (D7 to D0) D3 D2 01 01 01 01 00 00 00 00 11 11 11 11 10 10 10 10 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Table 7-1-3 (5) Address (HEX) Command (HEX) (A7 to A0) 10 F2 Function (*: Setting at reset) Focus gain at the frequency set at 750 Hz Approx. value 3.92 dB Approx. value 3.36 dB Approx. value 2.80 dB Approx. value 2.24 dB Approx. value 1.68 dB Approx. value 1.12 dB Approx. value 0.56 dB Approx. value 0 dB Approx. value 1.05 dB Approx. value 2.11 dB Approx. value 3.16 dB Approx. value 4.21 dB Approx. value 5.27 dB Approx. value 6.32 dB Approx. value 7.37 dB Approx. value 8.43 dB (Setting for tracking system) Data (D7 to D0) D7 D6 D5 D4 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 Address (HEX) (A7 to A0) Command (HEX) 10 F2 Table 7-1-3 (6) Function (*: Setting at reset) Tracking gain at the frequency set at 1 kHz Approx. value 3.92 dB Approx. value 3.36 dB Approx. value 2.80 dB Approx. value 2.24 dB Approx. value 1.68 dB Approx. value 1.12 dB Approx. value 0.56 dB Approx. value 0 dB Approx. value 1.05 dB Approx. value 2.11 dB Approx. value 3.16 dB Approx. value 4.21 dB Approx. value 5.27 dB Approx. value 6.32 dB Approx. value 7.37 dB Approx. value 8.43 dB SDD00025AEM 28 MN662790RSC (D) Setting for anti-vibration (VSET) The gain-up amount and gain-up time can be set when VDET=H. (VDET can be monitored through the VDETMON pin.) Table 7-1-3 (7) Data (D7 to D0) D2 0 0 0 0 1 1 1 1 D5 0 0 0 0 1 1 1 1 D7 D6 00 01 10 11 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Address (HEX) Command (HEX) (B7 to B0) (A7 to A0) 11 F2 Function (*: Setting at reset) Setting of the focus gain-up amount at vibration Scale factor 1.0 (0 dB) Scale factor 1.125 ( 1.0 dB) Scale factor 1.25 ( 1.9 dB) Scale factor 1.375 ( 2.8 dB) Scale factor 1.5 ( 3.5 dB) Scale factor 1.625 ( 4.2 dB) Scale factor 1.75 ( 4.9 dB) Scale factor 2.0 ( 6.0 dB) Setting of the tracking gain-up amount at vibration Scale factor 1.0 (0 dB) Scale factor 1.125 ( 1.0 dB) Scale factor 1.25 ( 1.9 dB) Scale factor 1.375 ( 2.8 dB) Scale factor 1.5 ( 3.5 dB) Scale factor 1.625 ( 4.2 dB) Scale factor 1.75 ( 4.9 dB) Scale factor 2.0 ( 6.0 dB) Setting of the gain-up time at vibration Time 23.2 ms Time 46.4 ms Time 92.9 ms Time 185.8 ms Note) The gain-up amount set by VSET is valid only when FC2 or FR2 for the focus system or TC2 or TR2 for the tracking system is written after VSET setting. (No operation is performed to set servo parameters in the anti-vibration mode only by VSET setting.) SDD00025AEM 29 MN662790RSC The gain values can be overwritten when VDET Data (D7 to D0) D7 D6 D 5 D4 D7 D6 D 5 D4 D3 D2 D1D0 D3 D2 D1D0 Address ( H EX ) (A7 to A0) 2D 2E H. Table 7-1-3 (8) Function Focus gain constant at vibration (FG2) (8-bit mantissa) (1 to 255) Focus gain constant at vibration (FEXP2) (8-bit exponent) (16, 32, 64 and 128 only) (Focus gain constant = mantissa / exponent) Tracking gain constant at vibration (TG2) (8-bit mantissa) (1 to 255) Tracking gain constant at vibration (TEXP2) (8-bit exponent) (16, 32, 64 and 128 only) (Tracking gain constant = mantissa / exponent) Setting values at reset 128 32 Command (HEX) (B7 to B0) F2 D7 D6 D 5 D4 D7 D6 D 5 D4 D3 D2 D1D0 D3 D2 D1D0 35 36 128 64 Note) Be aware that the gain set with VSET applies at the time of fine gain adjustment and writing data to the FC2, FR2, TC2 or TR2. SDD00025AEM 30 MN662790RSC (E) Various system settings (E)-1 SET0 setting Data (D7 to D0) D3 D2 00 01 10 11 Address (HEX) Command (HEX) (B7 to B0) (A7 to A0) 12 0 0 0 0 1 1 1 1 F2 Table 7-1-3 (9) Function (*: Setting at reset) Setting of forced brake operation time OFF ON (5.8 ms) ON (11.6 ms) ON (23.2 ms) Setting of convergence gain during tracking balance adjustment 1/2048 1/4096 1/1024 1/8192 D6 0 0 1 1 D4 0 1 0 1 0 0 0 0 1 1 1 1 D5 0 1 01 01 Tracking balance adjustment output As usual Inverted polarity D7 0 1 01 01 TVD output smoothing OFF ON TVD output Example of the TVD intermittent drive is as follows. Smoothing OFF TVD Smoothing ON TVD 2.9 ms 2.9 ms 2.9 ms 2.9 ms SDD00025AEM 31 MN662790RSC (E)-2 SET1 setting Table 7-1-3 (10) Data (D7 to D0) D0 Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) 13 F2 Function (*: Setting at reset) TVD output at the time of kick pulse output in the traverse stop condition TVD output No TVD output Pull-in method when turning focus ON from OFF state Conventional method High-speed pull-in High-speed kickback ON/OFF ON OFF Focus offset adjustment method With vibration Without vibration Focus offset adjustment method direction (Same as MN66271) direction D1 D2 D4 D5 D6 D3 Standby time after TCNT 50 ms 100 ms 0 ms 10 ms DAC output limiter (FABC, TABC) D7 OFF ON SDD00025AEM 32 MN662790RSC (E)-3 SET2 setting Table 7-1-3 (11) Data (D7 to D0) D1 D0 14 F2 Address (HEX) (A7 to A0) Command (HEX) (B7 to B0) Function (*: Setting at reset) Traverse dead-zone amp Normal (Type A) side only (Type B) side only (Type C) Tracking offset adjustment standby time None 30 ms Convergence judgement condition for tracking balance adjustment 2 LSBs at TBAL output stage 1 LSB at TE input stage Focus balance adjustment convergence gain 18 14 1 32 1 16 Disc detection, focus rough gain adjustment frequency 5.4 Hz 2.6 Hz Traverse intermittent drive Output enabled Output disabled D2 D3 D5D4 D6 D7 DED0 D ED 0 2 DED0 2 Figure 1 Traverse dead-zone amp Type A Figure 2 Traverse dead-zone amp Type B Figure 3 Traverse dead-zone amp Type C Note) Refer to 7-1 (4) (F)-6 for the DED0 setting. SDD00025AEM 33 MN662790RSC (E)-4 SET3 setting Table 7-1-3 (12) Data (D7 to D0) D1 D0 1E F2 Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) Function (*: Setting at reset) TVD gain variable 0 dB ( 1.0) 3.5 dB ( 1.5) 6.0 dB ( 2.0) 2.5 dB ( 0.75) Cancellation of focus balance adjustment Reset to the initial value at the start of adjustment The adjusting value is on hold Tracking rough gain adjustment time 134 ms 319 ms Focus search mode As usual Amplitude: 1/4 Offset readjustment after tracking fine gain adjustment Performed automatically Not performed Focus balance adjustment output As usual Inverted polarity Focus search frequency 1.3 Hz 2.6 Hz D2 D3 D4 D5 D6 D7 SDD00025AEM 34 MN662790RSC (E)-5 SET5 setting Table 7-1-3 (13) (Setting of vibration detection band-pass filter constant) Address Data Command (HEX) (HEX) (D7 to D0) (B7 to B0) (A7 to A0) D 1D 0 15 F2 Function (*: Setting at reset) Setting of LPF 2nd stage constant C 3 4 5 6 Setting of LPF 1st stage constant B 3 4 5 6 Setting of HPF constant A 3 4 5 6 Vibration detection level exponent part 1 Note) Refer to 7-1 (4) 2 (F)-11 for the 4 setting of mantissa 8 part. D 3D 2 D5D4 D7D6 1/2 TRE Vibration detection signal (VDET) -1 -1 -1 -1 Detection level 1-2 / 256 HPF A 1-2 / 256 1-2 / 256 LPF 1st stage LPF 2nd stage SDD00025AEM 35 MN662790RSC (E)-6 SETTB setting Table 7-1-3 (14) Data (D7 to D0) D0 Address Command (HEX) (HEX) (B7 to B0) (A7 to A0) 4A F2 Function (*: Setting at reset) Tracking brake damping reinforcement Damping reinforcement mode 1 Damping reinforcement mode 2 Low-band compensation during tracking brake operation Ye s No Tracking brake timing Reference at 1/4-track-before Reference at zero cross Dropout countermeasure during KICK operation No Ye s Brake timing countermeasure with OFT noise filter turned on No Ye s Hunting countermeasure for focus balance adjustment No Ye s Tracking brake noise elimination Ye s No D1 D2 D3 D5 D6 D7 Damping Reinforcement Damping is reinforced by changing the level of KICK pulses, which is set with the KICK2, with servo control turned on in KICK operation. Mode 1: The inverted pulse in full brake speed control and servo control is set as KICK2. Mode 2: In addition to the condition in mode 1, the inverted pulse drive after the target track is passed is also set as KICK2. Refer to 7-1 (4) (F)-9 for the KICK pulse level setting. SDD00025AEM 36 MN662790RSC (E)-7 Software reset The servo processing is initialized if data of AAh address is accessed. DSP processing starts with the first address. Table 7-1-3 (15) Data (D7 to D0) Address (HEX) (A7 to A0) AA Command (HEX) (B7 to B0) F2 Function (*: Setting at reset) Software reset (Data is disabled.) (E)-8 Forced gain-up setting The LSI can be in forced gain-up mode by accessing the data of 81h address. This mode is reset by accessing the data in 80h address. Table 7-1-3 (16) Data (D7 to D0) Address (HEX) (A7 to A0) 81 Command (HEX) (B7 to B0) F2 Function (*: Setting at reset) Focus / tracking forced gain-up (Data is disabled.) Focus / tracking normal gain (Data is disabled.) 80 Note) The VDET monitor signal is not set to H when the forced gain-up command is issued. The status of the VDET can be monitored through the VDETMON pin. The output of the VDETMON pin varies from H to L when vibration is detected even in the forced gain-up mode. Then, this mode is not reset. SDD00025AEM 37 MN662790RSC (F) Optical servo system setting Table 7-1-3 (17) Address (8 bits) 18 (F)-1 Focus search setting Data (8 bits) 0 D6 D5 D4 D3 D2 D1 D0 Command (HEX) (B7 to B0) F2 Function Focus search amplitude (CRAM2) setting 8-bit data (p-p) (40 to 127) Focus search/disc detection direction (SD) setting 8-bit data (0, 1) (0: Reducing FOD) Setting at reset 45 D0 19 0 Note 1) In focus search/disc detection direction setting, a value of SD will change automatically according to execution of a focus search/disc detection. Consequently, the values written by initial setting and DTMS may have changed when they are read out with DTSM. If you want to perform a focus search/disc detection from the same direction every time, it is necessary to set with DTMS every time before the focus search/disc detection. To make SD settings, check the SD value with the DTSM so that no bit values other than the set bit value will change. (F)-2 Setting of tracking servo fail-safe value (CRAM3) Data (8 bits) 0 D6 D5 D4 D3 D2 D1 D0 Table 7-1-3 (18) Function Fail-safe value clip level 8-bit data (0 to 127) Low-band component of drive output in the tracking brake mode is clipped at the specified value. Address (8 bits) 1C Command (HEX) (B7 to B0) F2 Setting at reset 72 (F)-3 Setting of disturbance amplitude (CRAM4) in tracking balance adjustment Data (8 bits) Address (8 bits) 1D Table 7-1-3 (19) Function Setting at reset 72 Command (HEX) (B7 to B0) F2 0 D6 D5 D4 D3 D2 D1 D0 Disturbance amplitude (one side) 8-bit data (0 to 127) Amplitude of the disturbance waves input in the tracking balance adjustment is set. Actual disturbance amplitude is 1/8 CRAM4. SDD00025AEM 38 MN662790RSC (F)-4 KICK setting Data (8 bits) D3 D2 D1 D0 Table 7-1-3 (20) Address (8 bits) 1A Command (8 bits) F2 Function KICK speed (KS) setting 4-bit data (6 to 15) KICK brake timing setting 4-bit data (0 to 15) Setting values at reset 6 D7 D6 D5 D4 0 TE cycle in the speed control mode is determined by the KICK speed setting. KS (D3 to D0) 22.6 s TE KICK brake output timing delay time is set in the KICK brake timing setting. (1 count 22.6 s delay) Setting value 0: No delay 1/4-track-before Brake Mode SETTB (address: 4Ah) D2=0 When OFT is turned to "L" after passing the position of 1/4 track OFT When OFT is turned to "L" before reaching a position of 1/4 track OFT 1/4 track TE Delay KICK Brake Zero Cross Brake Mode OFT SETTB (address: 4Ah) D2=1 TE Delay KICK Brake TE Delay KICK Brake SDD00025AEM 39 MN662790RSC (F)-5 Traverse drive constant in tracking brake (TVG) Data (8 bits) D 3 D2 D1 D0 Table 7-1-3 (21) Function Traverse drive constant TVG (1 to 15) Only in the tracking brake, traverse will be driven with the traverse error multiplied by the required constant. Address (8 bits) 1B Command (8 bits) F2 Setting at reset 2 (F)-6 Traverse drive dead zone setting (DED0) Data (8 bits) Address (8 bits) 1F Table 7-1-3 (22) Function Traverse drive dead zone setting (one side) DED0 (0 to 127) Command (8 bits) F2 Setting at reset 24 0 D6 D5 D4 D3 D2 D1 D0 (F)-7 TE noise elimination width setting at track count/kick (SETKC) Data (8 bits) Address (8 bits) 49 Table 7-1-3 (23) Function Setting at reset 3 Command (8 bits) F2 0 D6 D5 D4 D3 D2 D1 D0 TE noise elimination width setting at track counting/kick SETKC (0 to 127) Target track TE SETKC When the TE gradient is inverted and reaches the level of the SETKC, braking completes. KICK (TRD) Brake SDD00025AEM 40 MN662790RSC (F)-8 KICK pulse width setting (KCCNT) Data (8 bits) Address (8 bits) 4B Table 7-1-3 (24) Function Inverted pulse width during servo pull-in operation in KICK operation. (Set value 22.6 11.3) s KICK pulse initial accelerating time (0 to 15) (Set value 22.6) s Command (HEX) (B7 to B0) F2 Setting at reset 1 D7 D6 D5 D4 D3 D2 D1 D0 5 TE Inverted pulse width KICK (TRD) Brake TE KICK (TRD) Initial accelerating time (F)-9 KICK pulse level setting (KICK and KICK2) Command Address (HEX) Data (8 bits) (8 bits) (B7 to B0) 78 F2 Table 7-1-3 (25) Function Setting KICK pulse level in normal operation KICK (0 to 127) Setting KICK pulse level during servo pull-in operation KICK2 (0 to 127) Setting at reset 84 0 D6 D5 D4 D3 D2 D1 D0 0 D6 D5 D4 D3 D2 D1 D0 7A 84 (F)-10 Traverse output gain setting (TRV) Data (8 bits) Address (8 bits) 79 Table 7-1-3 (26) Command (HEX) (B7 to B0) F2 Function Traverse output gain setting TRV (0 to 127) Setting at reset 95 0 D6 D5 D4 D3 D2 D1 D0 SDD00025AEM 41 MN662790RSC (F)-11 VDET detecting level setting Data (8 bits) D 7 D 6 D5 D 4 D 3 D 2 D 1 D 0 Table 7-1-3 (27) Command (HEX) (B7 to B0) F2 Address (8 bits) 7B Function VDET detection TE threshold level setting (mantissa part) VSLT (1 to 255) Setting at reset 57 Threshold level exponent part (Refer to 7-1 (4) (E)-5.) SET5 [D7, D6] threshold level VSLT TE 0 0 0 1 1 0 1 0 1 VSLT VSLT VSLT VSLT 1 2 4 8 VDET (F)-12 Number of disturbance waves in fine gain adjustment (PHSU) Data (8 bits) D7 D6 D5 D4 D3 D2 D1 D0 Table 7-1-3 (28) Function Setting at reset 129 Address Command (HEX) (8 bits) (B7 to B0) 7C F2 Number of disturbance waves in fine gain adjustment (See Note.) PHSU (1 to 255) Note) The convergence gain increases as the number of disturbance waves increases. (F)-13 Setting of convergence gain in fine gain adjustment (PDK) Data (8 bits) D2 0 0 0 0 1 1 1 1 D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 5 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Table 7-1-3 (29) Function Setting at reset 66 Address Command (HEX) (8 bits) (B7 to B0) 61 F2 Convergence gain in Fo fine gain adjustment 1 2 4 8 16 32 64 128 Convergence gain in Tr fine gain adjustment 1 2 4 8 16 32 64 128 SDD00025AEM 42 MN662790RSC (F)-14 Setting of automatic adjustment range The limits of adjustment values can be set arbitrarily in the range of 1/128 to 255/16 (or 42 dB to 24 dB). In order to ensure automatic gain convergence within a limited, narrow adjustment range to prevent excessive gain change, which has difficulty in convergence control, however, make sure that the maximum automatic adjustment range is 9 dB on the basis of the gain set value. Tracking gain Automatic adjustment range GLT3/GLT4 to GLT1/GLT2 Table 7-1-3 (30) Command (HEX) (B7 to B0) F2 Data (8 bits) Address (8 bits) Function Tracking gain upper limit GLT1 (mantissa) (128 to 255) GLT2 (exponent) (128, 64, 32, 16) Tracking gain lower limit GLT3 (mantissa) (128 to 255) GLT4 (exponent) (128, 64, 32, 16) Setting at reset 181 32 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3D 3E D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3F 40 91 128 GLT1 and GLT3 can be both set to 127 or a smaller value only if GLT2 and GLT4 are both set to 128. Focus gain Automatic adjustment range Data (8 bits) GLF3/GLF4 to GLF1/GLF2 Address (8 bits) Command (HEX) (B7 to B0) F2 Table 7-1-3 (31) Function Setting at reset 181 16 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 39 3A Focus gain upper limit GLF1 (mantissa) (128 to 255) GLF2 (exponent) (128, 64, 32, 16) Focus gain lower limit GLF3 (mantissa) (128 to 255) GLF4 (exponent) (128, 64, 32, 16) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3B 3C 181 128 GLF1 and GLF3 can be both set to 127 or a smaller value only if GLF2 and GLF4 are both set to 128. SDD00025AEM 43 MN662790RSC [3] Access command setting Table 7-1-3 (32) Data (16 bits) D15 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 KICK-count setting 0 (other than 0) Command (8 bits) 11110001 Function KICK-count setting/KICK operation start Inner track KICK operation Outer track KICK operation Track-count setting / Track counting start Inner track counting Outer track counting D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Track-count setting 11110011 Note) The track-count means the number of tracks until the brake operation start point is reached. SDD00025AEM 44 MN662790RSC 7-1 (4) Data setting in signal processing section (A) Audio output control (I) Data (16 bits) D1 D0 00 01 10 11 D2 0 1 D4 D3 0 10 11 D6 D5 0 01 11 D7 0 1 D9 0 1 D11 D10 00 01 10 11 D12 0 1 D13 0 1 D15 0 1 Table 7-1-4 (1) Address (8 bits) 01000001 Function (*: Setting at reset) Available for bilingual Normal stereo L-ch monaural R-ch monaural L-/R-ch reverse D/A converter output polarity Normal Inverse Emphasis control Control by DEMPH output Forced OFF Forced ON Peak detection L-ch, R-ch L-ch R-ch CLV synchronization stabilized status detection flag control Accepted at 64 counts of IPFLAG Accepted at 32 counts of IPFLAG SRDATA de-emphasis control Not controlled Controlled CD-TEXT control Not controlled CD-TEXT mode 1 CD-TEXT mode 2 CD-TEXT mode 3 CD-TEXT CRC operation control CRC operation result output TEXT data position flag output in BLKCK TEXT data output byte control in CD-TEXT mode 3 TEXT data 16-byte output TEXT data 18-byte output CD-TEXT mode 4 control Not controlled CD-TEXT mode 4 SDD00025AEM 45 MN662790RSC (B) Digital audio interface control Table 7-1-4 (2) Data (16 bits) D3 0 0 0 1 D1 D0 00 10 11 Address (8 bits) 01000010 Function (*: Setting at reset) Bit U control of TX output LDON control Bit U enabled Bit U fixed to "H" Mute control (Bit U is fixed to "H" with DMUTE pin set to "H" or with SRDATA mute command.) Generation status bit control of TX output Generation status bit 0 Generation status bit 1 TX mute control Mute OFF Mute ON TX Bit V mode selection (during interpolation) Bit V is ON Bit V is not ON D2 0 1 D4 0 1 D5 0 1 D6 0 1 D7 0 1 TX data selection DF input data As usual TX Bit V mode selection (during ATT) Bit V is ON Bit V is not ON SDD00025AEM 46 MN662790RSC (C) General-purpose I/O port control The general-purpose I/O port has four pins, which are GIO0 through GIO3 pins. The default settings of the GIO0 and GIO3 pins are for the input signals SQCK and RSEL of the LSI respectively. Command execution makes it possible to make general-purpose I/O port settings of the GIO0 and GIO3 pins. Unlike the GIO0 and GIO3 pins, the GIO1 and GIO2 pins work as output ports at the time of LSI resetting. The GIO1 and GIO2 pins have low-level output. Command execution makes it possible to make general-purpose I/O port settings and CLDCK and FCLK output signal settings of the LSI. Note) Do not apply middle-level input if these pins are used as general-purpose input ports. Table 7-1-4 (3) Data (16 bits) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0 1 10 0 1 10XXXX Address (8 bits) 01000011 Function (*: Setting at reset) Default setting Port output value setting 0: Output value at "L" 1: Output value at "H" (Enabled when the port is set as output port.) Port designation address GIO0 designation GIO1 designation GIO2 designation GIO3 designation Port output value setting enabled or disabled Port output value setting disabled Port output value setting enabled Port I/O mode setting 0: Input port 1: Output port Function selection mode setting 0: LSI I/O mode 1: General-purpose I/O port mode Mode setting enabled or disabled 0: I/O mode setting and function selection mode setting disabled 1: I/O mode setting and function selection mode setting enabled RF signal polarity control RF polarity bright level "L" RF polarity bright level "H" X X X X X X X X X X X X XXXXXXXXX0 XXXXXXXXX1 D2 D1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D3 X X X X X X X X X X X X XXXXXX XXXXXX XXX XXX X X X X X X X X X X D7 D6 D5 D4 X X G IO3 G IO2 G IO1 G IO0 X X X X X X X D11 D10 D9 D8 X G IO3 G IO2 G IO1 G IO0 X X X X X X X X D 15 0X 1X X X X X X X X X XXXXXXXXXX XXXXXXXXXX X X D14 0X 1X X X X X X X XXX XXX XX XXX XX XXX XX XX If D15 disables mode setting, the command is disabled except the port output signal level setting data. Therefore, changes in the output signal level are made with ease. After all settings, the input signals (or output signals if the port is so set) of the GIO3 through GIO0 pins are output from the STAT pin in series. The signals are output in synchronization with the falling edge of the MCLK as shown in the following timing chart. SDD00025AEM 47 MN662790RSC 01000011 MDATA MCLK MLD STAT output General-purpose I/O port output timing GIO3 GIO0 GIO1 GIO2 GIO3 Data NOP SDD00025AEM 48 MN662790RSC (D) Spindle control Table 7-1-4 (4) Data (16 bits) D10 0 0 0 0 D10 0 0 0 0 D10 0 0 D10 0 0 D10 0 0 D8 0 1 D7 0 1 D3 0 1 D4 0 0 1 1 D2 0 0 1 1 D1 0 1 0 1 D0 0 1 0 1 Address (8 bits) 01000101 Function (*: Setting at reset) f0 frequency setting f 0 24 H z f0 6 Hz f 0 12 H z f0 3 Hz Spindle gain setting Normal gain Gain 6 dB Gain 12 dB Gain 6 dB 4x-speed playback mode setting 4x-speed playback mode canceled 4x-speed playback mode setting SRF/EFM input selection SRF input EFM input PC pin polarity setting When spindle monitor output is ON, PC pin=L. When spindle monitor output is ON, PC pin=H. Jitter-free mode OFF ON PLL phase comparison output (PLLF) ON OFF (Only when tracking is OFF) STAT output selection OFF (Normal ) ON (FCLV RESY) Power-down mode setting Normal mode Power-down mode (DF/DAC clock stopped) D11 D10 00 10 D12 0 1 D13 0 1 D14 0 1 D10 0 0 D10 0 0 D10 0 0 Note) f0 frequency: Considering the gain crossover point to be fV, the point shown on the right is described as f0. Phase component Velocity component f0 fV SDD00025AEM 49 MN662790RSC (E) Audio output control (II) Data (16 bits) D0 0 1 D6 0 1 D3 0 1 D4 0 1 D5 0 1 D7 0 1 D2 D1 00 11 Table 7-1-4 (5) Address (8 bits) 01000110 Function (*: Setting at reset) Correction CPU reset control Not controlled Reset C2 correction selection C2 triple correction C2 quadruple correction CLDCK output duty control Normal 50 % output duty SRDATA attenuation control Not controlled Attenuation ( 12 dB) PCK and EFM output control Normal output PCK and EFM output fixed to L CK384 control (at IOSEL=L) CK384 output (Xtal) 384fs output for signal processing (VCO output in jitter-free mode) D8 0 1 Spindle gain-down No gain-down 3.5 dB (One per three ECS outputs is not output.) EDATA flag selection FLAG0 IPFLAG Serial data mute control Mute OFF Mute ON DF/DAC output mute Mute OFF Mute ON PLL pull-in mode selection 12T detection output width: 64 PCK 12T detection output width: 32 PCK D9 0 1 D 10 0 D11 0 1 D12 0 Note) Set the C2 correction selection to the triple correction mode for audio CD playback. Note) When using C2 quadruple correction, set the selection (2T or 5T) of 4Dh command PLL detection to 2T. SDD00025AEM 50 MN662790RSC Data (16 bits) D14 D13 00 0 10 11 D15 0 Address (8 bits) 01000110 Function (*: Setting at reset) PLLF2 pin control (on-chip switch) Forced OFF Forced ON ON with RESY set to "H" ON with RESY set to "L" PCK pin output mode PLL clock output DSL balance output Table 7-1-4 (6) (F) Audio output control (III) Data (16 bits) D11 0 0 D5 0 0 D0 0 1 Address (8 bits) 01000111 Function (*: Setting at reset) RFDET processing control of servo CPU RFDET normal processing Data processed as L-level signal regardless of input STAT output selection (with output selected with MCLK) OFF (Normal) ON (FLOCK RFDET) DSLBDA pin output mode Not controlled DSLB DAC output SUBQ output control (SSEL H) MSB-first output LSB-first output in the unit of byte Oscillation stop control (See Note.) Normal Oscillation stop DSL balance compensation circuit setting Operation stop (with output on hold) Compensation value retrieval TRV pin intermittent drive control Normal mode (continuous drive) Intermittent drive (at 44.1 kHz) DSL offset function with Tr OFF With DSL offset With no DSL offset LSI clock control Clock enabled Clock disabled Power down control Not controlled VCO, A/D, DF/DAC disabled D11 0 0 D5 0 0 D1 0 1 D11 0 0 D11 0 0 D11 0 0 D11 0 0 D11 0 0 D11 0 0 D11 0 0 D11 D10 00 01 D9 0 1 D8 0 D7 0 D5 D2 0 1 D3 0 1 D5 0 0 D5 D4 00 01 D6 D5 00 0 D5 0 0 D5 0 0 D5 0 0 D5 0 0 Note) Oscillation stop control can be reset with RST. SDD00025AEM 51 MN662790RSC Data (16 bits) D13D12 D11 000 010 110 D14 0 1 D11 0 0 D5 0 0 0 D5 0 0 Address (8 bits) 01000111 Function (*: Setting at reset) Track cross operation control Not controlled Noise elimination at 4 MHz Noise elimination at 2 MHz KICK pulse width control Not controlled Controlled (G) CLV speed setting Table 7-1-4 (7) Data (16 bits) Address (8 bits) Function (*: Setting at reset) Setting of variable pitch data (D9 to D0) 0 51.1 (maximum value) 51.2 (minimum value) Variable pitch selection Variable pitch OFF Variable pitch ON ON/OFF setting of VCO oscillation for variable pitch control (See Note.) VCO oscillation OFF VCO oscillation ON D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 0 1 0000000000 0010000000 1101111111 D10 0 1 D 11 0 1 D 11 1 D 12 0 1 D13 0 1 Disc rotation speed judgement data setting (in jitter-free mode) 8-bit data DF/DAC clock lock setting Normal Locked VCO charge pump current source control Current ON Current OFF Note) In jitter-free mode, turn VCO on. SDD00025AEM 52 MN662790RSC (H) DSL and PLL control (I) Data (16 bits) D1 0 0 1 1 D3 D2 00 01 10 11 D5 D4 00 01 1 D6 0 1 D7 0 1 Table 7-1-4 (8) Address (8 bits) D0 0 1 0 0 1 0 1 1 0 1 0 1 Function (*: Setting at reset) PLLF current selection 1 1.25 0.5 0.75 PLLF current selection (Linked with value 1 set in D1 and D0) 1.25 0.5 0.75 OFT noise filter control Not controlled Control mode 1 Control mode 2 VCO control Pitch control and servo VCO operation VCO stopped PLL frequency-dividing control (See Note.) Not controlled Controlled D6 of address 4Bh and D11 of address 49h are available to a command each for controlling the VCO for pitch control and/or that for servo use. Refer to the following for available control modes according to the command. 4Bh D6 (VCO control) 49h D11 (Pitch control VCO oscillation) Pitch control VCO Servo VCO Oscillation Stop Oscillation Oscillation Stop Stop Note) In principle, set the bit to 1 to enable PLL frequency-dividing control. SDD00025AEM 53 MN662790RSC (I) DSL and PLL control (II) Table 7-1-4 (9) Data (16 bits) D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 00 01 01 01 D7 0 1 0 0 D6 0 0 1 0 D5 0 1 1 0 D4 0 1 0 D1 D0 0 1 1 D2 0 1 Stop PLL gain control Normal mode (Tracking OFF Gain-up at ON) Gain-up mode PLL 2T or 5T detection selection 2T 5T PLL pull-in mode selection 2T and 5T detecting output width 32 PCK 44 PCK 52 PCK 64 PCK 0 1 Address (8 bits) 01001101 Function (*: Setting at reset) Dropout operation (CLV) (PLL) Enable Enable Stop (DSL) Enable Stop 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note) The following formula is available for setting 2T and 5T detecting output widths. 2T or 5T detecting output width = D8 32 D7 16 D6 8 D5 4 4 Note) When using C2 quadruple correction, set the selection (2T or 5T) of 4Dh command PLL detection to 2T. SDD00025AEM 54 MN662790RSC (J) DIGTAL PLL control Table 7-1-4 (10) Data (16 bits) D2 D1 D0 000 1 D3 0 1 D5 0 0 1 1 D6 0 1 D7 0 1 D8 0 1 D9 0 1 D10 0 1 D4 0 1 0 1 1 1 Address (8 bits) 01001110 Function (*: Setting at reset) Increment/Decrement counter limit setting Limit value 14 (See Note.) Limit value 0 Increment/Decrement counter clear mode setting 1/2 Cleared to be 0. PCK delay value setting PCK delay 0 PCK delay 1 clock PCK delay 2 clock PCK delay 3 clock Resolution selection 1/8 1/16 VCO oscillation frequency selection 67 MHz 138 MHz PCK generation PLL selection Analog PLL Digital PLL VCO selection Pitch control and jitter-free Digital PLL Digital PLL operating frequency setting Normal 2 Note) Limit value 8 D2 4 D1 2 D0 When the VCO is set to digital PLL use (i.e., D9 of the above command is set to 1), pitch control or jitter-free function is not available. SDD00025AEM 55 MN662790RSC (K) STAT pin control Table 7-1-4 (11) Data (16 bits) Unnecessary for this command (8 bits) 0 0 0 0 0 0 0 0 0 D2 D1 0 0 1 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01110110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 Address (8 bits) Function (*: Setting at reset) STAT pin output CRC STCNT CLVS TTSTOP (TTOFF) JCLVS (TTON) SQOK FCLV SUBQ SYFLG ED A TA STAT pin output setting STAT pin output FLAG6 SENSE FLOCK (RFDET) TLOCK 0 1 1 10 10 1 Control of FLAG6 output from STAT pin NOP Reset of FLAG6 Disc rotation speed data output from STAT pin Frame memory address reset OFF Frame memory address reset ON SDD00025AEM 56 MN662790RSC 7-1 (5) Automatic adjustment Following is a list of automatic adjustment. Command B7 B6 B5 B4 B3 B2 B1 B0 Fo/Tr offset AOC Description Table 7-1-5 Time Traverse required operation Averages and corrects the focus error values and 50 ms FWD/ to tracking error values as offset when the laser is REV 140 ms enabled turned on or off. Fo balance ABC1 Inputs the disturbance into the focus servo loop, Within 0.5 s and make corrections so that the envelope ripple for the 3T component of the RF signal in the positive and negative parts of the FE signal should be balanced. The output pin for corrections is FBAL. The average tracking error value without the tracking servo is used as a balancing value to make corrections. The output pin for corrections is TBAL. Focus search is performed at approx. 5.4 Hz or 1.3 Hz, and the disturbance input amount for the fine AGC is determined by using focus error Scurve [P-P] value. The gain will be unchanged. Within 1s STOP Tr balance ABC2 STOP Fo rough gain AGC1 Tr rough gain AGC2 Fo fine gain FAGC Tr fine gain TAGC FWD/ Set between REV 190 ms enabled and 780 ms Set between 135 ms and 350 ms The [P-P] value of the tracking error in the tracking servo off status determines the disturbance input amount for the fine AGC. The gain will be unchanged. STOP Inputs the disturbance into the focus servo loop, Within 0.5 s and adjusts the gain crossover to the frequency set by the microcomputer command. STOP Inputs the disturbance into the tracking servo loop, and adjusts the gain crossover to the frequency set by the microcomputer command. Within 0.5 s STOP Note) If focus balance adjustment is stopped due to automatic adjustment stoppage or focus failure, only the next focus pull-in operation will be delayed. In order to prevent this phenomenon from occurring, it is necessary to write "0" to D2 of the SD (19F2h) after focus balance adjustment (i.e., after checking that the SENSE is set to low level). For SD settings, refer to page 38. SDD00025AEM 57 MN662790RSC 7-2. I/O timing 7-2 (1) Serial data output When LRCK "L"AFR-ch When LRCK "H" L-ch LRCK BCLK SRDATA R-ch IPFLAG (Audio-I) R-ch 0 15 0 15 MSB L-ch L-ch LS B R-ch IPFLAG (Audio-II) L-ch Upper 8 bits t1 L-ch Lower 8 bits Figure 7-2-1 LRCK, BCLK, SRDATA and IPFLAG output timing The value of t1 is 11.34 s at normal-speed, 5.67 s at 2x-speed and 11.34 s when the pitch controller is used. (100 + shift amount) 100 BCLK BYTCK SRDATA 13 14 15 R-ch 01234567 8 9 10 11 12 13 14 15 LS B L-ch MSB IPFLAG L-ch Lower L-ch Upper Figure 7-2-2 Output timing in CD-ROM mode SDD00025AEM 58 MN662790RSC 7-2 (2) Serial data output with de-emphasis function ON t R-ch L- c h LRCK BCLK SRDATA D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D7 D6 D5 D4 D3 D 2 D1 D0 D 15 D 14 D 13 D12 D 11 D10 D 9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Disabled data MSB MSB LSB Disabled data (0.75t) LSB (0.75t) Disabled data Figure 7-2-3 LRCK, BCLK and SRDATA output timing with de-emphasis function ON The SRDATA signal is output at 32 fs and the LSB data after each LRCK change includes 0.25t disabled data. The phase relation with the IPFLAG is not guaranteed. 7-2 (3) Serial data input format The input data for the DF + DAC section can be given from the outside by setting the IOSEL pin to the L level. When this is done, give an LRCK input through the MSEL pin, BCLK input through the SSEL pin and SRDATA input through the PSEL pin. At this time, the internal settings of the conventional MSEL, SSEL and PSEL pins will be MSEL = L, SSEL = H and PSEL = L, respectively. The LRCK input frequency is fixed at 44.1 kHz. When the 2x-speed mode or jitter-free is used, a serial data input is not available in other than the DF/DAC clock fixed mode, because the performance of a D/A converter audio output is not assured. (See Table 7-1-38.) The BCLK input can be arbitrarily set between 16 and 32 clocks per half an LRCK cycle. However, LRCK should be changed synchronously with the falling edge of BCLK. The SRDATA input is an MSB-first, 2's complement type input. It should be changed synchronously with the falling edge of BCLK. Also, check that the contents of the SRDATA are L-ch data when LRCK is at the H level. As described above, the number of BCLK clocks can be 17 or more for each sampled data. If this is the case, the contents of the SRDATA should be back-aligned with respect to an LRCK change point, and LRCK must change before the rising edge of the next BCLK signal, after sampling the LSB of the SRDATA at the rising edge of BCLK. D/A converter output muting, D/A converter output polarity switching, emphasis control and peak detection DF output mode can be applied to a serial data input from an external source. Bilingual switching only works on a serial data output, not on a serial data input. SDD00025AEM 59 MN662790RSC LRCK Input BCLK Input SRDATA 4 3 2 1 0 Input R-ch 16 Clocks to 32 Clocks Don't care 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB L-ch LS B R-ch L Figure 7-2-4 LRCK input (MSEL), BCLK input (SSEL) and SRDATA input (PSEL) timing when IOSEL SDD00025AEM 60 MN662790RSC 7-2 (4) Subcode interface A. Read SUBQ data You can read subcode data in two ways according to the setting of the SSEL pin. The timing is shown in Figure 7-2-5. When SSEL=L: When SSEL pin is at L level, this LSI and the microcomputer serve as master and slave, respectively, to read SUBQ data. BLKCK and CLDCK are output at fixed frequencies of 75 Hz and 7.35 kHz, respectively. SUBQ output varies in synchronization with the falling edge of CLDCK output. The microcomputer receives SUBQ output at the timing of the rising edge of CLDCK output. If the CRC output is OK, it is processed as correct data. The result of CRC check can be read by CRC or STAT pin. The content of SUBQ is output as follows: S0 and S1 signals are output in synchronization with BLKCK output. Then, 80-bit subcode data are output. Then 8-bit peak detection data on the left or right channel is output twice continuously. When SSEL=L, SUBQ output is inverse one. When SSEL=H: When SSEL pin is at H level, this LSI and the microcomputer serve as slave and master, respectively, to read SUBQ data. The LSI receives an output signal from the microcomputer regardless of CLDCK output, and changes SUBQ output. Then, by entering 96 clocks of SQCK, all SUBQ output can be read. The microcomputer starts the interrupt operation at the rising edge of BLKCK output. First, it checks the result of CRC of SUBQ output. If it is OK, SQCK is input to read SUBQ data. The contents of SUBQ are synchronized with the rising edge of BLKCK. First, a CRC result is output, and then, 80-bit subcode data are output every falling edge of SQCK. Then 8-bit peak detection data on the left or right channel is output twice continuously. At SSEL = H, SUBQ output is positive one. By inputting the microcomputer command 000847h as shown in Table 7-1-4 (6), subcode data in the unit of byte is output beginning with the LSB at every falling edge of SQCK. Read subcode data from STAT with command By inputting the microcomputer command 78H as shown in Table 7-1-4 (11), subcode data can be read from STAT pin in synchronization with the falling edge of MCLK on condition that the SSEL pin is at H level. This mode is available only immediately after issuance of the microcomputer command 78h. This mode is cancelled when other commands are issued. SDD00025AEM 61 MN662790RSC When SSEL=L (SUBQ output is inverse one): BLKCK CLDCK SUBQ S0 S1 Q1 Q2 Q3 Q4 Q79 Q80 L15 R8 S0 S1 Q1 CRC STAT (=CRC) DEMPH H: CRC=OK L: CRC=NG H: CRC=OK L: CRC=NG H and L for all data are inverted. When SSEL=H: BLKCK CLDCK SQCK SUBQ CRC Q 1 Q2 Q 3 Q4 Q 79 Q 80 L 15 R10 R9 R8 CRC CRC STAT (=CRC) H: CRC=OK L: CRC=NG H: CRC=OK L: CRC=NG DEMPH SQOK 8.7 ms Figure 7-2-5 BLKCK, CLDCK, SQCK, SUBQ, CRC and DEMPH timing SDD00025AEM 62 MN662790RSC When SSEL BLKCK H: (When microcomputer command 000847h is input) CLDCK SQCK SUBQ CRC Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q16 Q15 Q73 L8 R15 CRC CRC STAT (=CRC) H: CRC=OK L: CRC=NG H: CRC=OK L: CRC=NG DEMPH SQOK B. Read subcode data 8.7 ms By inputting a clock from SBCK pin, subcode data, P to W, can be read from SUBC pin. The timing is shown in Figure 7-2-5. Since subcode data varies every falling edge of CLDCK, input 8 clocks of SBCK every falling edge of CLDCK, and switch the content of SUBC output to P to W. Then you should receive SUBC output which varies in synchronization with the falling edge of SBCK at the timing of the rising edge of SBCK. You can read all subcode data by repeating the operation above for each CLDCK. By inputting SBCK, the content of FLAG output will change. So you cannot measure the error rate when reading subcode. You must consider it in system designing. Use of SQOK Signal Usually the BLKCK signal is used as a trigger to start reading SUBQ data. The data is output from the SUBQ pin in synchronization with the SQCK signal. The necessary bits of data (i.e., usually 80 bits) need to be read before the next BLKCK signal output is turned on. The SQOK signal is set to H level for approximately 8.7 ms in the first half of the BLKCK-synchronous period. There is no need to finish reading the data while the SQOK is at H level. The SQOK signal is used for reading SUBQ data without using BLKCK interruption. The SQCK signal is monitored by software scanning and the reading of SUBQ data is started on detection of the H-level signal. At that time, the data must be read for a maximum approx. 2 ms because the period until the next BLKCK signal output is turned on is approx. 4.6 ms. SDD00025AEM 63 MN662790RSC Typ. 136 s BLKCK CLDCK Typ. 1.5 s SBCK SUBC S0 S1 P1 to W1 P2 to W2 P3 to W3 P4 to W4 P5 to W5 P6 to W6 P7 to W7 CLDCK Min. 400 ns Min. 400 ns SBCK Min. 1 s SUBC P Q R S T U V W Max. 300 ns Max. 300 ns Figure 7-2-6 CLDCK, SUBC and SBCK timing SDD00025AEM 64 MN662790RSC 7-2 (5) EDATA error rate monitor function The error rate can be monitored through the STAT pin. The error rate is the number of frames (FLAG0=H), where C1 errors are detected, out of 2048 frames of data. The rate monitored is within an output range between 0 and 255. By changing the command, the number of interpolation flag (IPFLAG) signals out of 2048 frames of data is monitored within an output range between 0 and 255. Flag definite delay Monitoring method tD=Max. 1.0 s MCLK MDATA 46h b9Al 7Ah MLD STAT Flag D7 D6 D5 D4 D3 D2 D1 D0 The EDATA output command 7Ah is input after setting the EDATA change command in 46h(b9). The flag must be checked after the point of the flag definite delay. If the flag is set to L level, there is no need to read the error rate data because the rate is the same as the error rate data previously read. Input the MCLK signal and read the error rate if the flag is set to H level. SDD00025AEM 65 MN662790RSC 7-2 (6) CD-TEXT interface CD-TEXT mode 1 BLKCK GIO3/RSEL (DQSY) tD= 23.0 ms 16 or 18 bytes SBCK SUBC When CRC error is occurred TEXT CRC or the top position flag CD-TEXT mode 2 BLKCK GIO3/RSEL (DQSY) SQCK SUBQ MCLK STAT SUBQ SUBQ CRC SUBQ SUBQ CRC Fixed to H TEXT CRC TEXT data TEXT CRC T EX T data TEXT CRC TEXT data TEXT CRC TEXT data Fixed to H SDD00025AEM 66 CD-TEXT M Mode 3 1.63 ms ( 2) Fix the SQCK pin to high level when the CD-TEXT mode 3 is used. MN662790RSC Original BLKCK BLKCK (DQSY) tD 3.0 s MCLK B C D Data A STAT Indefinite Indefinite Indefinite Indefinite MDATA 78 MLD SDD00025AEM This command starts data reading with STAT. This command need not be set again unless any other command is issued. 22 or 20 bytes CD-TEXT (18 or 16 bytes) command selection SUBQ (3 bytes) (Contents of Data) Status (1 byte) Note) In data D , only single-byte header of SUBQ data is valid. D3 D2 D1 D0 CD-TEXT data CRC (or 1's flag in position B above) SUBQ data CRC Start pack flag (set to 1 in position A above only) CLVS or RESY TLOCK FLOCK SENSE FLAG6 D7 D6 D5 D4 67 (Mode 3 Command Issuance) The command needs to be set again if commands other than 78h are issued because such commands clear the TEXT and SUBQ data settings of STAT pin. MN662790RSC Case 1: Command issuance at the end of data reading End of reading 22 or 20 bytes BLKCK MCLK Command MDATA 78h Status byte + TEXT data + SUBQ data MLD STAT 22 or 20 bytes in total Case 2: Command issuance before data reading BLKCK SDD00025AEM MCLK Command MDATA 78h MLD STAT It is impossible to determine whether this is for command issuance or data reading purpose. 22 or 20 bytes in total Case 3: Command issuance while data reading BLKCK MCLK Command MDATA 78h MLD STAT 68 MN662790RSC CD-TEXT Mode 4 Internal BLKCK BLKCK SQCK SU B Q SUBQ MCLK MDATA MLD SU B Q CRC TE X T C R C TE X T data TE X T C R C TEX T data TEXT CRC TEXT data TEXT CRC TEX T data SU B Q C R C Mode 4 setting Mode 4 released Mode 4 must be released before the rising edge of BLKCK. SDD00025AEM 69 MN662790RSC 7-2 (7) Digital PLL setting For an improvement in playability of this LSI, a digital PLL circuit is built in so that the LSI will be in stable operation without being influenced by digital noise. The lock range of this PLL circuit is not as wide as an analog PLL circuit. Therefore, a system controller is required with an analog PLL circuit employed so that the analog PLL circuit will be used in access operation and switched over to the digital PLL circuit at the end of the access operation. The digital PLL is available in normal- and 2x-speed playback modes. The following mode combinations can be set. Data D10 D7 D6 Address 4E Function Digital PLL operating frequency Resolution VCO oscillation frequency 0 0 0 Normal-speed playback 1 1/8 67 MHz 1 1 0 2 1/16 67 MHz 1 0 0 2x-speed playback 2 1/8 67 MHz 1 1 1 2 1/16 138 MHz Use the SYFLG (i.e., the CLV synchronous establishment detecting flag) in the following sequence to switch over the analog PLL circuit to digital PLL circuit. Kick Kick ARF Q read Q read Access end judgement STAT (SYFLG) SYFLG at H level detected IPFLAG Digital PLL set command issued Note 1) Change the digital PLL circuit over to the analog PLL circuit at the start point of the access operation. Change the digital PLL circuit over to the analog PLL circuit when the reading of the Q-code fails while the LSI is in PLAY operation. Use a sequence like the one shown above to change the digital PLL circuit over to the analog PLL circuit. Note 2) The SYFLG can be used in playback mode after a short track jump, such as a single-track jump, or a kick. In that case, make sure that the Q-code is read properly in a sequence like the one shown above after the track jump or kick is performed. SDD00025AEM 70 MN662790RSC 7-2 (8) Video CD setting It is desirable to increase the probability of correction rather than decrease the probability of error correction for video CD in playback mode. Therefore, set the C2 correction to quadruple correction. Set the C2 correction to triple correction when playing back an audio CD. Data D6 D2 D1 Address 46 Function Selection of C2 correction 1 1 1 Video CD Quadruple correction 0 0 0 Audio CD Triple correction 7-2 (9) Digital audio interface Bit V control D7 and D5 of microcomputer command address 42h are used for the Bit V control of the digital audio interface. Data (16 bits) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address (8 bits) 42h Function (*: Setting at reset) TX Bit V change (in interpolation mode) Bit V ON Bit V OFF TX Bit V change (in ATT mode) Bit V ON Bit V OFF Note 1) The LSI in ATT mode means that the LSI is in digital attenuation, soft attenuation, or soft muting mode. The Bit V is, however, always off if the LSI is under 12 dB control for serial data attenuation with D4 of 46h set to on. If the Bit V is set to off in ATT mode for a TX Bit V change, the Bit V is on when the digital or soft attenuation level is set to 0 (i.e., dB). Note 2) The Bit V is always on in TX mute control or mute control through the DMUTE pin. 7-2 (10) Audio output MUTE The microcomuputer command makes it possible to mute SRDATA output, DF/DAC output, or TX output independently. All outputs can be muted through the DMUTE pin. SRDATA DMUTE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address pin output L 46 42 DF/DAC output TX output MUTE OFF MUTE OFF MUTE OFF MUTE ON MUTE OFF MUTE OFF MUTE OFF MUTE OFF MUTE OFF MUTE OFF MUTE OFF MUTE ON MUTE OFF MUTE ON MUTE OFF MUTE ON MUTE ON MUTE ON H SDD00025AEM 71 MN662790RSC 7-2 (11) Error correction This LSI performs double correction for the C1 decoder and triple correction/quadruple correction for the C2 decoder. For the C2 decoder, when the data is judged impossible to correct or not highly reliable (having a high probability of erroneous correction or overlooking), it is interpolated by the interpolation circuit. (In the case of audio mode I) For the C1 and C2 decoders, correction results are output from the FLAG pin as FLAG0 to FLAG5. When the C1 decoder detects an error for FLAG0, "H" is output for approx. 4.6 s, starting from the rising edge of FCLK. FLAG1 to FLAG6 are output from FLAG pin in synchronization with the falling edge of SBCK input from the outside. SDD00025AEM 72 MN662790RSC Flag Output Timings (At Normal-Speed) 136 s (7.35 kHz) FCLK 354 Min. 0 ns ns SBCK Min. 1 s FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG0 Min. 400 ns Min. 400 ns FLAG 4.6 s Max. 300 ns Max. 300 ns 4.6 s If the falling edge of clock is input to SBCK while FLAG0 is being output, an output from FLAG pin will be switched from FLAG0 to FLAG1. SDD00025AEM 73 MN662790RSC PRODUCT STANDARDS A. ABSOLUTE MAXIMUM RATINGS Parameter A1 A2 A3 A4 Supply voltage 5-V reference voltage Input voltage Output voltage Symbol VDD AVDD VCC5V VI VO VSS AVSS VSS AVSS Rating 0.3 to +4.6 0.3 to +5.7 0.3 to VDD+0.3 0.3 to AVDD+0.3 0.3 to VDD+0.3 0.3 to AVDD+0.3 580 Unit V V V V Ta = 25 Note VSS=0 V AVSS=0 V VSS=0 V AVSS=0 V VSS=0 V AVSS=0 V VSS=0 V AVSS=0 V VSS=0 V AVSS=0 V Ta = 85 (Note 7) A5 Power dissipation PD mW A6 A7 Operating ambient temperature Storage temperature Topr Tstg 30 to +85 55 to +125 Note 1) The absolute maximum ratings are the limit values beyond which the device may be broken. They do not assure operations. Note 2) Each of VSS, DVSS1, AVSS1 and AVSS2 pins should be directly connected to the ground and used at the same voltage. Note 3) Each of VDD, DVDD1, AVDD1 and AVDD2 pins should be directly connected to the specified power supply and used at the same voltage. Note 4) VDD, DVDD1, AVDD1 and AVDD2 should be powered up at the same time. Note 5) Connect a bypass capacitor (0.1 F or more) between VDD and VSS pins, between DVDD1 and DVSS1 pins, between AVDD1 and AVSS1 pins, between AVDD2 and AVSS2 pins and between VREF and VSS pins. Note 6) The operation of the audio D/A converter is guaranteed only for operation in normal-speed playback mode. Note 7) Condition: This LSI shall be mounted on a standard glass epoxy board (75 mm 75 mm 0.8 mm). SDD00025AEM 74 MN662790RSC B. OPERATING CONDITIONS Ta 30 to 85 ,VSS 0 V AVSS 0 V Unit min B1 B2 B3 B4 B5 Note 9) Digital system supply voltage Analog system supply voltage Digital system supply voltage Analog system supply voltage 5-V reference voltage VDD AVDD VDD1 AVDD1 VCC5V Normal-and 2x-speed playback modes Normal-and 2x-speed playback modes 4x-speed playback mode 4x-speed playback mode 3.0 3.0 3.2 3.2 4.75 Limits Parameter Symbol Conditions typ 3.3 3.3 3.3 3.3 5.0 max 3.6 3.6 3.6 3.6 5.25 V V V V V It is recommended to basically use AVDD at the same voltage as DVDD. Self-excited Oscillation 1 (Note 10) B6 B7 B8 Crystal frequency External capacitance 1 External capacitance 2 fxtal C1 C2 CSEL L Ta 30 to 85 ,VSS 0 V VDD 3.3 V, AVSS 0 V 16.9344 5 5 MHz pF pF External Clock Input 1 (Note 11), (Note 12) B9 B10 B11 B12 B13 Clock input frequency Clock input amplitude High-level pulse width Low-level pulse width External capacitance 3 fX1 VX1 tX1H tX1L C3 CSEL L C3 1000 pF Switching level VX1/2 2.0 26 26 1000 29.5 29.5 16.9344 MHz V[P-P] ns ns pF External Clock Input 2 (Note 11), (Note 12) B14 B15 B16 B17 B18 Clock input frequency Clock input amplitude High-level pulse width Low-level pulse width External capacitance 3 fX1 VX1 tX1H tX1L C3 CSEL H C3 1000 pF Switching level VX1/2 2.0 13 13 1000 14.8 14.8 33.8688 MHz V[P-P] ns ns pF SDD00025AEM 75 MN662790RSC Ta 30 to 85 ,VSS 0 V VDD 3.3 V, AVSS 0 V Note 10) Oscillation circuit C2 X2 MN662790RSC X1 C1 Xtal The appropriate capacitors' values differ according to the oscillator used. Use the values specified by the oscillator manufacturer. Note 11) External clock input 1 X2 MN662790RSC X1 OPEN C3 External clock Note 12) External clock 1 / fX1 VX1/2 VX1 tX1H tX1L SDD00025AEM 76 MN662790RSC VCC5V 5.0 V VSS 0 V AVDD VDD, AVSS 0 V Ta 30 to 85 fX1 16.9344 MHz Limits Parameter Symbol Conditions min C1 Supply current Total power consumption Supply current IDD Ptot I DD VDD=3.3 V No external load during normalspeed playback mode Ta=25 fX1=16.9344 MHz CSEL=L VDD=3.3 V No external load during 2xspeed playback mode Ta=25 fX1=16.9344 MHz CSEL=L When DF/DAC clock fixed mode is set. t yp 45 max 1 00 mA mW mA Unit C. Electrical Characteristics (1) DC Characteristics C2 C3 150 50 330 103 C4 Total power consumption Ptot 170 340 mW C5 Supply current IDD C6 Total power consumption VDD=3.3 V No external load during 4xspeed playback mode Ta=25 fX1=16.9344 MHz CSEL=L When DF/DAC clock fixed mode is set. 60 105 mA Ptot 200 345 mW SDD00025AEM 77 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Input Pins (1) Input voltage C7 high level Input voltage C8 low level C9 Input leakage current 1 VIH1 VIL1 ILK1 VIN 0 to VDD 0.7VDD 0 VDD 0.3VDD 1 V V A typ max Unit fX 1 Input Pins (2) Input voltage C10 high level C11 Input voltage low level C12 Input leakage current Input Pin (3) Input voltage C13 high level C14 Input voltage low level C15 Input leakage current 1 2 2 VIH2 VIL2 I LK2 VIN 0 to VCC5V 2.0 0 VCC5V 0.8 1 V V A SBCK VIH3 VIL3 I LK3 VIN 0 V to 5.25 V 2.0 0 5.25 0.8 1 V V A TEST3, OFT, RFDET, BDO, TEST, IOSEL MCLK, MDATA, MLD, SQCK/GIO0, DMUTE, RST, RSEL/GIO3, CSEL, PSEL, SSEL, MSEL SDD00025AEM 78 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Output Pins (1) Output voltage high level Output voltage C17 low level C16 Output Pins (2) Output voltage high level Output voltage C19 low level C18 C20 Output leakage current (ECM) 3 VOH1 VOL1 4 VOH2 VOL2 ILK2 IOH2 2.0 mA VDD 0.6 f X1 Unit typ max I O H1 2.0 mA VDD 0.6 V 0.4 V IOL1 2.0 mA V 0.4 1 V A IOL2 2.0 mA Hi-Z Vo 0 V to 3.3 V 3 BCLK, LRCK, SRDATA, SENSE, FLOCK, SUBQ, STAT, SMCK, PC, LDON, WVEL, EFM, PCK, SUBC, BYTCK/TRVSTP, GIO1/CLDCK, GIO2/FCLK, IPFLAG, CLVS, CRC, DEMPH, TX, BLKCK, FLAG, RESY/FLAG6 ECM 4 SDD00025AEM 79 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits min Analog System Input Pin (1) C21 Input current IREF fX1 Parameter Symbol IREF When pulled up by a 120-k resistor Conditions Unit max typ 11 20 28 A Analog System Input Pin (2) C22 Input signal amplitude C23 Input leakage current VARF ILKA ARF Input level of the EFM signal in the application circuit of the DSL circuit block 0.5 1.0 1 V[P-P] A Analog System Input Pin (3) C24 Input leakage current Internal resistance ILKA RDRF DRF 1 2x-speed playback mode ARF 1.65 V 10 A k C25 between ARF and DRF pins Analog System Output Pin (1) DSLF (IREF pin is pulled up to AVDD by a 120-k C26 Output current (N) C27 Output current (P) C28 current Output unbalance IDSH BDO L, Tracking ON-state DSLF 1.65 V, ARF 3.3 V BDO L, Tracking ON-s tate DSLF 1.65 V, ARF 0 V 45 59 resistor) (Note 13) 75 A IDSL 45 7.0 59 1.0 75 5.0 A A IDSH+IDSL DSLF 1.65 V Normal current output mode Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD by a 120-k C29 output current (N) C30 output current (P) C31 Phase comparison Phase comparison IPFH IPFL IPFH+IPFL ILKP1 BDO BDO L, Tracking OFF-state L, Tracking OFF-state 52 52 8.55 67 67 2.55 resistor) 89 89 4.45 1 A A A A Phase comparison output unbalance current BDO L, Tracking OFF-state Normal current output mode Hi-Z Normal-speed playback mode (With IREF pin as shown in the recommended circuit diagram) C32 Leakage current C ci C33 VeqOeoscyllation fr u n 1 fVCO1 3.71 4.92 MHz SDD00025AEM 80 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits min typ max Unit fX1 Parameter Symbol Conditions Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD by a 120-k C34 frequency 2 C35 frequency 3 VCO oscillation fVCO2 2x-speed playback mode (With IREF pin as shown in the recommended circuit diagram) 4x-speed playback mode (With IREF pin as shown in the recommended circuit diagram) resistor) 9.84 MHz 7.42 VCO oscillation fVCO3 14.84 25.93 MHz Analog System Output Pin (3) VCOF (IREF pin is pulled up to AVDD by a 120-k C36 output current (N) Phase comparison C37 output current (P) C38 Input leakage current Jitter-free VCO Phase comparison IVFH IVFL ILKV Hi-Z With IREF pin as shown in the recommended circuit diagram (4x-speed mode) With IREF pin as shown in the recommended circuit diagram (2x-speed mode) With IREF pin as shown in the recommended circuit diagram (Normal-speed mode) resistor) 71 71 1 A A A 40 40 54 54 19.6438 33.8688 50.8032 9.8219 4.9109 16.9344 25.4016 8.4672 12.7008 MHz C39 oscillation frequency fVCO4 Analog System Output Pin (4) PLLF2 (IREF pin is pulled up to AVDD by a 120-k C40 Leakage current C41 Internal resistance between PLLF and PLLF2 pins resistor) 1 A ILKP2 RPLLF PLLF 1.65 V 250 Analog System Input Pin (4) C42 Input signal amplitude C43 Input leakage current VTRC ILKT TRCRS TRCRS signal input level (with VREF level as a center) 2 1 V[P-P] A Analog System Output Pin (5) VCOF2 (IREF pin is pulled up to AVDD by a 120-k C44 output current (N) C45 output current (P) Phase comparison Phase comparison IVFH2 IVFL2 ILKV2 fVCO5 Hi-Z With IREF pin as shown in the recommended circuit diagram 33.8688 40 40 54 54 71 71 1 resistor) A A A MHz C46 Input leakage current VCO oscillation C47 frequency SDD00025AEM 81 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 t o 85 16.9344 MHz or 33.8688 MHz fX1 VDD 68 k IREF 0.022 F VARF 1.0 V[P-P] (typ.) 0.001 F ARF 27 k 100 k DRF DSLF 100 k 0.068 F PLLF 330 1200 pF 0.33 F PLLF2 220 k PCK / DSLB VCOF* 2.7 k 0.33 F VCOF2 2.7 k 0.33 F Recommended Circuit Diagram to DSL / PLL and Jitter-free VCOF Blocks * When 4x-speed playback mode with a 16.9344-MHz clock or a jitter-free function is not used, connect the VCOF pin to VDD or ground. * It is necessary to change a value of the resistor connected to IREF pin to adjust the oscillation frequency in 4xspeed playback mode. Note 13) Note 14) Insert a 100-k resistor between the DSLF and PCK / DSLB pins or between the DSLF and DSLBDA pins to use the DSL balance correction function. This recommended circuit is typical, so it is necessary to choose external components' values with due regard to playability. 82 SDD00025AEM MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Analog System Input Pins (5) Input voltage C48 high level Input voltage C49 low level V I H4 VIL4 VREF 0.5AVDD fX1 Unit typ max TE, FE, RFENV AVDD 0 V V Analog System Input Pin (6) C50 Input voltage V I5 V Analog System Output Pins (6) Load C51 characteristic TVD, TRD, FOD, TBAL, FBAL, ECS, DSLBDA Load: 300 A Difference from no load state at 20 %, 50 % and 80 % of fullscale. V O4 4.0 LSB SDD00025AEM 83 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min A/D Converter Desired Values (for Servo) C52 C53 C54 Resolution Integral nonlinearity Differential nonlinearity RES INL DNL A/D output=80 to 7F (2's complement ) 8 2 3 bit LSB LSB t yp max Unit f X1 D/A Converter Desired Values (for Servo) C55 Resolution C56 C57 C58 C59 C60 Integral nonlinearity Differential nonlinearity Offset Offset Offset RES INL DNL Digital input 0 (2's complement) DOFF1 Value to 1.65-V output 8 2 0.82 10 10 10 bit LSB LSB LSB LSB LSB No load Value at 25 % of the full-scale DOFF2 No load DOFF3 Value at 75 % of the full-scale No load SDD00025AEM 84 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 t o 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min D/A Converter Desired Values Analog Characteristics C61 Signal to noise ratio C62 Dynamic range C63 C64 Total harmonic distortion Crosstalk S/N D.R. THD+N fX1 Unit t yp max (Note 15), (Note 18) 90 80 97 88 0.007 70 1.12 80 1.32 1.55 0.013 dB dB % dB Vrms EIAJ EIAJ EIAJ EIAJ f=1 kHz Full-scale output (Note 16) Difference of OUTL and OUTR pins at output level 1. 20 log (VR/VL) f=1 kHz Full-scale output (Note 17) C65 Output level 1 C66 Output level difference 0.99 0.99 dB C67 Output level 2 0.68 0.79 0.93 Vrms Note 15) The analog characteristics indicate the values measured by inserting a 15- resistor between the AVDD1 pin and power supply. The typical values are only reference values. They are not guaranteed. The output level 1 shows the measured value at the output pins of the application circuit. The output level 2 shows a value at the output pin of this LSI and is calculated by taking the measured value of output level 1, dividing it by the external circuit gain of the application circuit. Use the D/A converter only in the normal-speed playback mode. Operation of the D/A converter cannot be guaranteed when it is used in the 2x-and 4x-speed modes. Note 16) Note 17) Note 18) SDD00025AEM 85 MN662790RSC DVDD AVDD2 AVDD1 15 1k 47 k 100 pF 2.2 k + + 0.0018 F 1 .5 k 0.001 F 47 k 22 F 47 k 47 k 100 pF 22 F 560 [D/A Converter Application Circuit] VDD DVDD1 AVDD2 AVDD1 1 F OUTL 47 F 100 F MN662790RSC SDD00025AEM AVSS1 OUTR 1k 47 k 22 F 47 k 47 k 100 pF 22 F 560 100 pF 1.5 k 2.2 k AVSS1 0.001 F 47 k VSS DVSS1 AVSS2 0.0018 F DVSS AVSS2 86 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter C68 Rise time C69 Fall time C70 Rise time C71 Fall time C72 Rise time C73 Fall time Symbol tRA tFA tRB tFB tRC tFC There should be no noise greater than 20 mV[P-P] in signal lines and power supply. Conditions min typ max 250 250 100 100 100 100 ns ns ns ns ns ns Unit fX1 MLD 0.8 VDD 0.2 VDD tRA tFA 0.8 VDD 0.2 VDD SBCK 0.8 VDD 0.2 VDD tRB tFB 0.8 VDD 0.2 VDD MCLK 0.8 VDD 0.2 VDD tRC tFC 0.8 VDD 0.2 VDD SDD00025AEM 87 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 t o 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Microcomputer Instruction Input Timing C74 Clock frequency C75 Clock pulse width C76 Data setup time C77 Data hold time C78 Delay time C79 Latch pulse width fMCLK tCH, tCL tDSU tDH t LD D tLDW 300 300 300 600 0.6 100 1 MHz ns ns ns ns s t yp max Unit f X1 1/f MCLK MCLK tCH tCL MDATA tDSU tDH MLD tLDD tLDW SDD00025AEM 88 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Subcode Interface (1) C80 Clock width C81 High-level pulse width Low-level C82 pulse width tCK tCKH tCKL tSBD tSD 1 400 400 300 300 s ns ns ns ns t yp max Unit fX1 C83 Delay time C84 Setup delay time tCK tCKL SBCK tCKH SUBC tSD CLDCK tSBD SDD00025AEM 89 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Subcode Interface (2) C85 Clock width C86 High-level pulse width Low-level C87 pulse width tSQ tSQH tSQL tSQD 500 200 200 150 ns ns ns ns t yp max Unit fX1 C88 Delay time tSQ tSQL tSQH SQCK SUBQ tSQD SDD00025AEM 90 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min D/A Output Interface 1 C89 Clock width High-level C90 pulse width Low-level C91 pulse width C92 Setup time C93 Hold time D/A Output Interface 2 C94 Clock width High-level C95 pulse width Low-level C96 pulse width C97 Setup time C98 Hold time D/A Output Interface 3 C99 Clock width C100 High-level pulse width Low-level C101 pulse width tBCLK tBCLKH tBCLKL 4x-speed playback mode tST t HD 15 15 tBCLK tBCLKH tBCLKL 2x-speed playback mode tST t HD 5 88.5 44.2 44.2 ns ns ns ns ns 30 30 tBCLK tBCLKH tBCLKL tST tHD 5 177 88.5 88.5 ns ns ns ns ns Normal-speed playback mode 70 70 5 354 177 177 ns ns ns ns ns t yp max Unit f X1 C102 Setup time C103 Hold time SDD00025AEM 91 MN662790RSC 5 D/A Output Interface tBCLK tBCLKL tBCLKH BCLK SRDATA LRCK tST tHD SDD00025AEM 92 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 to 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min D/A Converter Input Timing C104 BCLK frequency C105 BCLK pulse width C106 Data setup time C107 Data hold time C108 LRCK frequency C109 BCLK-LRCK timing fBCLK tCH, tCL tDSU t DH fLRCK tBL, tLB 1/f BCLK f X1 Unit typ max 4 70 70 70 44.1 70 MHz ns ns ns kHz ns BCLKIN tCH tCL SRDATAIN tDSU tDH LRCKIN tBL tLB tBL tLB 1/f LRCK SDD00025AEM 93 MN662790RSC VCC5V 5.0 V VDD 3.3 V, VSS V AVDD 3.3 V, AVSS 0 V Ta= 30 t o 85 16.9344 MHz or 33.8688 MHz Limits Parameter Symbol Conditions min Reset Timing (Note 19) C110 RST pulse width C111 Rise time tNRSTL tRD 200 100 s ns t yp max Unit fX1 Power Supply Ripple Noise (Note 20) C112 Ripple amplitude C113 Ripple noise amplitude Note 19) VRIP V NZ 15 50 mV[P-P] mV[P-P] When the power is turned on, reset with the RST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within 10 % of error of the specified oscillation frequency. tNRSTL 0.8 VDD 0.2 VDD tRD 0.2 VDD RST Note 20) The standard ripple noise values of the LSI are guaranteed on condition that the values apply to typical 50-Hz to 100-Hz ripples with 500-kHz typical noise and that both the ripples and noise are in sine waveform as shown below. The values, however, vary under the influence of other parts located on the PCB. Therefore, be sure to check the actual values before applying the LSI to practical applications. Noise frequency 500 kHz VRIP VNZ Ripple frequency 50 Hz to 100 Hz SDD00025AEM 94 MN662790RSC Package Dimensions (Unit: mm) * LQFP080-P-1414A (lead-free package) 16.000.20 14.000.20 60 61 41 40 (0.825) 14.000.20 80 1 (0.825) 0.65 0.300.05 20 0.13 M 21 1.70 max. 1.400.10 (1.00) 0.150.05 0.100.10 16.000.20 0 to 10 0.500.20 0.10 Seating plane SDD00025AEM 95 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL |
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